AS7C33128NTD32B Datasheet, PDF (1/18 Pages) Alliance Semiconductor Corporation – 3.3V 128Kx32/36 Pipelined SRAM with NTD

February 2005
AS7C33128NTD32B
AS7C33128NTD36B
®
3.3V 128K×32/36 Pipelined SRAM with NTD^TM
Features
• Organization: 131,072 words × 32 or 36 bits
• NTD^™ architecture for efficient bus operation
• Fast clock speeds to 200 MHz
• Fast clock to data access: 3.0/3.5/4.0 ns
• Fast OE access time: 3.0/3.5/4.0 ns
• Fully synchronous operation
• Asynchronous output enable control
• Available in 100-pin TQFP package
• Byte write enables
• Clock enable for operation hold
• Multiple chip enables for easy expansion
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate V_DDQ
• Self-timed write cycles
• Interleaved or linear burst modes
• Snooze mode for reduced power standby
Logic block diagram
A[16:0]
17
CE0
CE1
CE2
R/W
BWa
BWb
BWc
BWd
ADV / LD
LBO
ZZ
D _AddressQ
register
Burst logic
CLK
Control
logic
CLK
DQ [a:d] ^32/36
D
Data Q
Input
Register
CLK
17
17
17
D
Q
Write delay
addr. registers
17
CLK
CLK
32/36
128K x 32/36
SRAM
Array
32/36
32/36
CLK
CEN
32/36
CLK
Output
OE ^Register
32/36
OE
DQ [a:d]
Selection Guide
Minimum cycle time
Maximum clock frequency
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
-200
-166
-133
5
6
7.5
200
166
133
3.0
3.5
4
375
350
325
135
120
110
30
30
30
Units
ns
MHz
ns
mA
mA
mA
2/8/05; v.1.5
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