AS7C33128NTD18B Datasheet, PDF (1/19 Pages) Alliance Semiconductor Corporation – 3.3V 128Kx18 Pipelined SRAM with NTD

April 2005
AS7C33128NTD18B
®
3.3V 128K×18 Pipelined SRAM with NTD^TM
Features
• Organization: 131,072 words × 18 bits
• NTD^™ architecture for efficient bus operation
• Fast clock speeds to 200 MHz
• Fast clock to data access: 3.0/3.5/4.0 ns
• Fast OE access time: 3.0/3.5/4.0 ns
• Fully synchronous operation
• Asynchronous output enable control
• Available in 100-pin TQFP package
• Byte write enables
• Clock enable for operation hold
• Multiple chip enables for easy expansion
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate V_DDQ
• Self-timed write cycles
• Interleaved or linear burst modes
• Snooze mode for standby operation
Logic block diagram
A[16:0]
17
CE0
CE1
CE2
R/W
BWa
BWb
ADV / LD
LBO
ZZ
D _Address Q
register
Burst logic
CLK
Control
logic
CLK
DQ [a:b]
18
D Data Q
Input
Register
CLK
CLK
CEN
17
17
D
Q
Write delay
addr. registers
17
CLK
CLK
128K x 18
SRAM
Array
18
18 18
18
CLK
Output
Register
OE
18
OE
DQ [a:b]
Selection Guide
Minimum cycle time
Maximum clock frequency
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
-200
-166
-133
Units
5
6
7.5
ns
200
166
133
MHz
3.0
3.5
4
ns
375
350
325
mA
135
120
110
mA
30
30
30
mA
4/28/05; v.1.3
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