AS7C33128FT32B Datasheet, PDF (1/19 Pages) Alliance Semiconductor Corporation – 3.3V 128K x 32/36 Flow Through Synchronous SRAM

February 2005
AS7C33128FT32B
AS7C33128FT36B
®
3.3V 128K × 32/36 Flow Through Synchronous SRAM
Features
• Organization: 131,072 words × 32 or 36 bits
• Fast clock to data access: 6.5/7.5/8.0/10.0 ns
• Fast OE access time: 3.5/4.0 ns
• Fully synchronous flow through operation
• Asynchronous output enable control
• Available in 100-pin TQFP package
• Individual byte write and Global write
• Multiple chip enables for easy expansion
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate V_DDQ
• Linear or interleaved burst control
• Snooze mode for reduced power standby
• Common data inputs and data outputs
Logic block diagram
CLK
ADV
ADSC
ADSP
A[18:0]
GWE
BWE
BW_d
BW_c
BW_b
BW_a
CE0
CE1
CE2
ZZ
OE
LBO
CLK
CE
Q0
Burst logic
CLR
Q1
128K × 32/36
19
D
Q ¹⁹
17
19
Memory
array
CE
Address
register
CLK
D _DQd Q
Byte write
registers
CLK
D _DQc Q
Byte write
registers
CLK
D _DQb Q
Byte write
registers
CLK
D _DQa Q
Byte write
registers
CLK
36/32
36/32
4
Power
down
D
Q
Enable
CE register
CLK
D _Enable Q
delay
register
CLK
OE
Output
buffer
Input
registers
CLK
36/32
DQ[a:d]
Selection guide
–65
-75
-80
Minimum cycle time
7.5
8.5
10
Maximum clock access time
6.5
7.5
8.0
Maximum operating current
275
250
215
Maximum standby current
90
85
75
Maximum CMOS standby current (DC)
30
30
30
-10
Units
12
ns
10.0
ns
185
mA
75
mA
30
mA
2/8/05; v.1.2
Alliance Semiconductor
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