AS7C32096A Datasheet, PDF (1/9 Pages) Alliance Semiconductor Corporation – 3.3V 256K x 8 CMOS SRAM

February 2005
Preliminary Information
®
AS7C32096A
3.3V 256K × 8 CMOS SRAM
Features
• Industrial and commercial temperature
• Organization: 262,144 words × 8 bits
• Center power and ground pins
• High speed
- 10/12/15/20 ns address access time
- 4/5/6/7 ns output enable access time
• Low power consumption: ACTIVE
- 650 mW / max @ 10 ns
• Low power consumption: STANDBY
- 28.8 mW / max CMOS
• Equal access and cycle times
• Easy memory expansion with CE, OE inputs
• TTL-compatible, three-state I/O
• JEDEC standard packages
- 44-pin TSOP 2
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
Logic block diagram
V_CC
GND
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
Input buffer
262,144 × 8
Array
(2,097,152)
Column decoder
Control
Circuit
I/O1
I/O8
WE
OE
CE
Pin arrangements
NC
NC
A0
A1
A2
A3
A4
CE
I/O1
I/O2
V_CC
GND
I/O3
I/O4
WE
A5
A6
A7
A8
A9
NC
NC
44-pin TSOP 2
1
44
2
43
3
42
4
41
5
40
6
39
7
38
8
37
9
36
10 35
11 34
12 33
13 32
14 31
15 30
16 29
17 28
18 27
19 26
20 25
21 24
22 23
NC
NC
NC
A17
A16
A15
A14
OE
I/O8
I/O7
GND
V_CC
I/O6
I/O5
A13
A12
A11
A10
NC
NC
NC
NC
Selection guide
–10
–12
–15
Maximum address access time
10
12
15
Maximum output enable access time
4
5
6
Maximum operating current
Industrial
180
160
140
Commercial 170
150
130
Maximum CMOS standby current
8
8
8
–20
Unit
20
ns
7
ns
110
mA
100
mA
8
mA
2/24/05, v. 1.0
Alliance Semiconductor
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