AS7C31026C Datasheet, PDF (1/10 Pages) Alliance Semiconductor Corporation – 3.3 V 64K X 16 CMOS SRAM

September 2006
Advance Information
AS7C31026C
®
3.3 V 64K X 16 CMOS SRAM
Features
• Industrial (-40^o to 85^oC) temperature
• Organization: 65,536 words × 16 bits
• Center power and ground pins for low noise
• High speed
- 10 ns address access time
- 5 ns output enable access time
• Low power consumption via chip deselect
• Upper and Lower byte pin
• Easy memory expansion with CE, OE inputs
• TTL-compatible, three-state I/O
• JEDEC standard packaging
- 44-pin 400 mil SOJ
- 44-pin TSOP 2-400
- 48-ball 6 × 8 mm BGA
• ESD protection ≥ 2000 volts
Logic block diagram
A0
A1
A2
A3
A4
A5
A6
A7
I/O0–I/O7
I/O8–I/O15
I/O
buffer
WE
V_CC
65,536 × 16
GND
Array
Control circuit
Address decoder
UB
OE
LB
CE
Pin arrangement
44-Pin SOJ (400 mil), TSOP 2
A4
1
A3
2
A2
3
A1
4
A0
5
CE
6
I/O0
7
I/O1
8
I/O2
9
I/O3
10
V_CC
11
GND
12
I/O4
13
I/O5
14
I/O6
15
I/O7
16
WE
17
A15
18
A14
19
A13
20
A12
21
NC
22
44
A5
43
A6
42
A7
41
OE
40
UB
39
LB
38
I/O15
37
I/O14
36
I/O13
35
I/O12
34
GND
33
V_CC
32
I/O11
31
I/O10
30
I/O9
29
I/O8
28
NC
27
A8
26
A9
25
A10
24
A11
23
NC
0000048 - BGA Ball-Grid-Array Package
1 2 3 45 6
A LB OE A₀ A₁ A₂ NC
B I/O8 UB A3 A4 CE I/O0
C I/O9 I/O10 A5 A6 I/O1 I/O2
D V_SS I/O11 NC
E V_DD I/O12 NC
F I/O14 I/O13 A14
A7 I/O3 V_DD
NC I/O4 V_SS
A15 I/O5 I/O6
G I/O15 NC A12 A13 WE I/O7
H NC A8 A9 A10 A11 NC
9/20/06, v 1.0
Alliance Memory
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