AS7C31025C Datasheet, PDF (1/9 Pages) Alliance Semiconductor Corporation – 3.3V 128K X 8 CMOS SRAM (Center power and ground)

September 2006
Advance Information
AS7C31025C
®
3.3V 128K X 8 CMOS SRAM (Center power and ground)
Features
• Industrial and commercial temperatures
• Organization: 131,072 x 8 bits
• High speed
- 10 ns address access time
- 5 ns output enable access time
• Low power consumption via ship deselect
• Easy memory expansion with CE, OE inputs
• Center power and ground
• TTL/LVTTL-compatible, three-state I/O
• JEDEC-standard packages
Logic block diagram
V_CC
GND
A0
A1
A2
A3
A4
A5
A6
A7
A8
Input buffer
I/O7
131,072 x 8
Array
(1,048,576)
I/O0
Address decoder
Control
circuit
WE
OE
CE
- 32-pin, 300 mil SOJ
- 32-pin, 400 mil SOJ
- 32-pin, TSOP 2
• ESD protection ≥ 2000 volts
Pin arrangement
32-pin TSOP 2
A0 1
A1 2
A2 3
A3 4
CE 5
I/O0 6
I/O1 7
V_CC 8
GND 9
I/O2 10
I/O3 11
WE 12
A4 13
A5 14
A6 15
A7 16
32 A16
31 _A15
30 _A14
29 _A13
28 _OE
27 _I/O7
26 _I/O6
25 _GND
24
23
V_CC
I/O5
22 _I/O4
21 _A12
20 _A11
19 _A10
18 A9
17 A8
32-pin SOJ (300 mil)
32-pin SOJ (400 mil)
A0
1
A1
2
A2
3
A3
4
CE
5
I/O0
6
I/O1
7
V_CC
8
GND
9
I/O2
10
I/O3
11
WE
12
A4
13
A5
14
A6
15
A7
16
32 ^A16
31 A15
30 A14
29 A13
28 OE
27 I/O7
26 I/O6
25 GND
24
V_CC
23 I/O5
22 I/O4
21 A12
20 A11
19 A10
18 A9
17 A8
9/20/06, v. 1.0
Alliance Memory
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