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AS7C31025B Datasheet, PDF (1/9 Pages) Alliance Semiconductor Corporation – 3.3V 128K X 8 CMOS SRAM (Center power and ground) | |||
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March 2004
AS7C31025B
®
3.3V 128K X 8 CMOS SRAM (Center power and ground)
Features
⢠Industrial and commercial temperatures
⢠Organization: 131,072 x 8 bits
⢠High speed
- 10/12/15/20 ns address access time
- 5, 6, 7, 8 ns output enable access time
⢠Low power consumption: ACTIVE
- 252 mW / max @ 10 ns
⢠Low power consumption: STANDBY
- 18 mW / max CMOS
⢠6 T 0.18 u CMOS technology
⢠Easy memory expansion with CE, OE inputs
⢠Center power and ground
⢠TTL/LVTTL-compatible, three-state I/O
⢠JEDEC-standard packages
- 32-pin, 300 mil SOJ
- 32-pin, 400 mil SOJ
⢠ESD protection ⥠2000 volts
⢠Latch-up current ⥠200 mA
Pin arrangement
Logic block diagram
VCC
GND
A0
A1
A2
A3
A4
A5
A6
A7
A8
Input buffer
I/O7
512 x 256 x 8
Array
(1,048,576)
I/O0
Column decoder
Control
circuit
WE
OE
CE
32-pin SOJ (300 mil)
32-pin SOJ (400 mil)
A0
1
A1
2
A2
3
A3
4
CE
5
I/O0
6
I/O1
7
VCC
8
GND
9
I/O2
10
I/O3
11
WE
12
A4
13
A5
14
A6
15
A7
16
32 A16
31 A15
30 A14
29 A13
28 OE
27 I/O7
26 I/O6
25 GND
24
VCC
23 I/O5
22 I/O4
21 A12
20 A11
19 A10
18 A9
17 A8
Selection guide
Maximum address access time
Maximum output enable access time
Maximum operating current
Maximum CMOS standby current
-10
-12
-15
-20
Unit
10
12
15
20
ns
5
6
7
8
ns
70
65
60
55
mA
5
5
5
5
mA
3/24/04, v. 1.3
Alliance Semiconductor
P. 1 of 9
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