AS7C31024B Datasheet, PDF (1/9 Pages) Alliance Semiconductor Corporation – 3.3V 128K X 8 CMOS SRAM

March 2004
®
3.3V 128K X 8 CMOS SRAM
AS7C31024B
Features
• Industrial and commercial temperatures
• Organization: 131,072 words x 8 bits
• High speed
- 10/12/15/20 ns address access time
- 5, 6, 7, 8 ns output enable access time
• Low power consumption: ACTIVE
- 252 mW / max @ 10 ns
• Low power consumption: STANDBY
- 18 mW / max CMOS
• 6T 0.18u CMOS technology
Logic block diagram
V_CC
GND
A0
A1
A2
A3
A4
A5
A6
A7
A8
Input buffer
512 x 256 x 8
Array
(1,048,576)
Column decoder
Control
circuit
• Easy memory expansion with CE1, CE2, OE inputs
• TTL/LVTTL-compatible, three-state I/O
• 32-pin JEDEC standard packages
- 300 mil SOJ
- 400 mil SOJ
- 8 × 20mm TSOP 1
- 8 x 13.4mm sTSOP 1
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
I/O7
I/O0
WE
OE
CE1
CE2
Pin arrangement
32-pin SOJ (300 mil)
32-pin SOJ (400 mil)
NC
1
A16
2
A14
3
A12
4
A7
5
A6
6
A5
7
A4
8
A3
9
A2
10
A1
11
A0
12
I/O0
13
I/O1
14
I/O2
15
GND
16
32
V_CC
31 A15
30 CE2
29 WE
28 A13
27 A8
26 A9
25 ^A11
24 OE
23 A10
22 CE1
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3
32-pin (8 x 20mm) TSOP I
32-pin (8 x 13.4mm) sTSOP1
A11 1
32
A9 2
31
A8 3
30
A13 4
29
WE 5
28
CE2 6
27
A15 7
26
V_CC
NC
A16
8
9
10
25
24
23
A14
11
22
A12
12
21
A7
13
A6
14
20
19
A5
15
18
A4
16
17
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
Selection guide
-10
-12
-15
-20
Unit
Maximum address access time
10
12
15
20
ns
Maximum output enable access time
5
6
7
8
ns
Maximum operating current
70
65
60
55
mA
Maximum CMOS standby current
5
5
5
5
mA
3/24/04, v.1.2
Alliance Semiconductor
P. 1 of 9
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