AS7C31024 Datasheet, PDF (1/9 Pages) Alliance Semiconductor Corporation – 5V/3.3V 128K x 8 CMOS SRAM (Evolutionary Pinout)

November 2000
®
5V/3.3V 128K×8 CMOS SRAM (Evolutionary Pinout)
AS7C1024
AS7C31024
Features
• AS7C1024 (5V version)
• AS7C31024 (3.3V version)
• Industrial and commercial temperatures
• Organization: 131,072 words × 8 bits
• High speed
- 10/12/15/20 ns address access time
- 5/6/8/10 ns output enable access time
• Low power consumption: ACTIVE
- 825 mW (c) / max @ 12 ns
- 360 mW (AS7C31024) / max @ 12 ns
• Low power consumption: STANDBY
- 55 mW (AS7C1024) / max CMOS
- 36 mW (AS7C31024) / max CMOS
• 2.0V data retention
• Easy memory expansion with CE1, CE2, OE inputs
• TTL/LVTTL-compatible, three-state I/O
• 32-pin JEDEC standard packages
- 300 mil SOJ
- 400 mil SOJ
- 8 × 20mm TSOP I
- 8 × 13.4 mm sTSOP I
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
Logic block diagram
V_CC
GND
Input buffer
A0
A1
A2
A3
512×256×8
A4
Array
A5
A6
(1,048,576)
A7
A8
Column decoder
Control
circuit
I/O7
I/O0
WE
OE
CE1
CE2
Pin arrangement
32-pin TSOP I
(8 x 20mm)
A11 1
A9 2
A8 3
A13 4
WE 5
CE2 6
A15
7
V_CC
NC
8
9
A16
10
A14
11
A12
12
A7
13
A6
14
A5
15
A4
16
32-pin SOJ (300 mil)
32-pin SOJ (400 mil)
32
31
30
OE
A10
CE1
NC
A16
1
2
29
I/O7 ^A14
3
28
I/O6 A12
4
27 I/O5 A7
5
26 I/O4 A6
6
25
I/O3 A5
7
24
23
22
21
20
GND _A4
I/O2 _A3
I/O1
I/O0
A0
A2
A1
8
9
10
11
19
A1
A0
12
18
A2 I/O0
13
17
A3 I/O1
14
I/O2
15
GND
16
32
V_CC
31 A15
30 CE2
29 _WE
28 _A13
27 _A8
26 A9
25 ^A11
24 OE
23 A10
22 _CE1
21 _I/O7
20 _I/O6
19 _I/O5
18 _I/O4
17 _I/O3
Selection guide
Maximum address access time
Maximum output enable access time
Maximum operating current
Maximum CMOS standby current
Shaded areas contain advance information.
AS7C1024-10 ^{AS7C1024-12 AS7C1024-15 AS7C1024-20}
AS7C31024-10 AS7C31024-12 AS7C31024-15 AS7C31024-20 Unit
10
12
15
20
ns
5
6
8
10
ns
AS7C1024
150
140
125
110
mA
AS7C31024
100
90
80
75
mA
AS7C1024
10
10
10
15
mA
AS7C31024
10
10
10
15
mA
11/29/00
ALLIANCE SEMICONDUCTOR
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