|
AS7C256A Datasheet, PDF (1/9 Pages) Alliance Semiconductor Corporation – 5V 32K X 8 CMOS SRAM (Common I/O) | |||
|
September 2004
AS7C256A
®
5V 32K X 8 CMOS SRAM (Common I/O)
Features
⢠Pin compatible with AS7C256
⢠Industrial and commercial temperature options
⢠Organization: 32,768 words à 8 bits
⢠High speed
- 10/12/15/20 ns address access time
- 5, 6, 7, 8 ns output enable access time
⢠Very low power consumption: ACTIVE
- 412.5 mW max @ 10 ns
⢠Very low power consumption: STANDBY
- 11 mW max CMOS I/O
⢠Easy memory expansion with CE and OE inputs
⢠TTL-compatible, three-state I/O
⢠28-pin JEDEC standard packages
- 300 mil SOJ
- 8 Ã 13.4 mm TSOP 1
⢠ESD protection ⥠2000 volts
⢠Latch-up current ⥠200 mA
⢠2.0V Data retention
Logic block diagram
VCC
GND
A0
A1
A2
A3
A4
A5
A6
A7
Input buffer
256 X 128 X 8
Array
(262,144)
Column decoder
AAAAAAA
8 9 10 11 12 13 14
Control
circuit
Pin arrangement
28-pin TSOP 1 (8Ã13.4 mm)
28-pin SOJ (300 mil)
I/O7
I/O0
WE
OE
CE
A14
1
OE
1
28
A10 A12
2
A11
2
A9
3
A8
4
27
26
25
CE
I/O7
I/O6
A7
A6
3
4
A13
5
24
I/O5
A5
5
WE
6
VCC
A14
7
8
23
22
I/O4
I/O3
A4
AS7C256A
21
GND A3
6
7
A12
9
A7
10
20
19
I/O2
I/O1
A2
8
A6
11
18
I/O0
A1
9
A5
12
A4
13
17
A0
16
A1
A0
10
A3
14
15
A2
I/O0
11
I/O1
12
I/O2
13
GND
14
28
VCC
27
WE
26
A13
25
A8
24
A9
23
A11
22
OE
21
A10
20
CE
19
I/O7
18
I/O6
17
I/O5
16
I/O4
15
I/O3
Selection guide
-10
-12
-15
-20
Unit
Maximum address access time
10
12
15
20
ns
Maximum output enable access time
5
6
7
8
ns
Maximum operating current
75
70
65
60
mA
Maximum CMOS standby current
2
2
2
2
mA
9/24/04; v.1.2
Alliance Semiconductor
P. 1 of 9
Copyright © Alliance Semiconductor. All rights reserved.
|
▷ |