AS7C25512PFD32A Datasheet, PDF (1/19 Pages) Alliance Semiconductor Corporation – 2.5V 512K x 32/36 pipelined burst synchronous SRAM

February 2005
AS7C25512PFD32A
AS7C25512PFD36A
®
2.5V 512K × 32/36 pipelined burst synchronous SRAM
Features
• Organization: 524,288 words × 32 or 36 bits
• Fast clock speeds to 166 MHz
• Fast clock to data access: 3.5/3.8 ns
• Fast OE access time: 3.5/3.8 ns
• Fully synchronous register-to-register operation
• Double-cycle deselect
• Asynchronous output enable control
• Available in 100-pin TQFP package
• Individual byte write and global write
• Multiple chip enables for easy expansion
• 2.5V core power supply
• Linear or interleaved burst control
• Snooze mode for reduced power-standby
• Common data inputs and data outputs
Logic block diagram
Selection guide
CLK
ADV
ADSC
ADSP
A[18:0]
GWE
BWE
BW_d
BW_c
BW_b
BW_a
CE0
CE1
CE2
ZZ
OE
19
Power
down
LBO
CLK
CE
CLR
Q0
Burst logic
Q1
D
Q ¹⁹
17
CE
Address
register
CLK
D _DQd Q
Byte write
registers
CLK
D _DQc Q
Byte write
registers
CLK
D _DQb Q
Byte write
registers
CLK
D _DQa Q
Byte write
registers
CLK
D
Q
Enable
CE register
CLK
D _Enable Q
delay
register
CLK
512K × 32/36
19
Memory
array
36/32
36/32
4
OE
Output
registers
CLK
Input
registers
CLK
36/32
DQ[a:d]
-166
Minimum cycle time
6
Maximum clock frequency
166
Maximum clock access time
3.5
Maximum operating current
290
Maximum standby current
85
Maximum CMOS standby current (DC)
40
-133
7.5
133
3.8
270
75
40
Units
ns
MHz
ns
mA
mA
mA
2/10/05, v. 1.2
Alliance Semiconductor
1 of 19
Copyright © Alliance Semiconductor. All rights reserved.