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AS7C25512NTF32A Datasheet, PDF (1/18 Pages) Alliance Semiconductor Corporation – 2.5V 512K x 32/36 Flowthrough Synchronous SRAM with NTD | |||
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April 2005
AS7C25512NTF32A
AS7C25512NTF36A
®
2.5V 512K Ã 32/36 Flowthrough Synchronous SRAM with NTDTM
Features
⢠Organization: 524,288 words à 32 or 36 bits
⢠NTD⢠architecture for efficient bus operation
⢠Fast clock to data access: 7.5/8.5/10 ns
⢠Fast OE access time: 3.5/4.0 ns
⢠Fully synchronous operation
⢠Flow-through mode
⢠Asynchronous output enable control
⢠Available in 100-pin TQFP package
⢠Individual byte write and global write
⢠Clock enable for operation hold
⢠Multiple chip enables for easy expansion
⢠2.5V core power supply
⢠Self-timed write cycles
⢠Interleaved or linear burst modes
⢠Snooze mode for standby operation
Logic block diagram
19
A[18:0]
CE0
CE1
CE2
R/W
BWa
BWb
BWc
BWd
ADV / LD
LBO
ZZ
D
Q
Address
register
Burst logic
CLK
Control
logic
CLK
DQ[a,b,c,d] 32/36
D Data
Input
Q
Register
CLK
CLK
CEN
Selection guide
-75
Minimum cycle time
8.5
Maximum clock access time
7.5
Maximum operating current
275
Maximum standby current
90
Maximum CMOS standby current (DC)
60
19
D
Q
Write delay
addr. registers
19
CLK
CLK
32/36
512K x 32/36
SRAM
Array
32/36 32/36
32/36
Output
Buffer
OE
32/36
OE
DQ[a,b,c,d]
-85
-10
10
12
8.5
10
250
230
80
80
60
60
Units
ns
ns
mA
mA
mA
4/21/05, v 1.2
Alliance Semiconductor
P. 1 of 18
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