AS7C252MNTD18A Datasheet, PDF (1/18 Pages) Alliance Semiconductor Corporation – 2.5V 2M x 18 Pipelined SRAM with NTD

January 2005
AS7C252MNTD18A
®
2.5V 2M × 18 Pipelined SRAM with NTD^TM
Features
• Organization: 2,097,152 words × 18 bits
• NTD^™ architecture for efficient bus operation
• Fast clock speeds to 200 MHz
• Fast clock to data access: 3.2/3.5/3.8 ns
• Fast OE access time: 3.2/3.5/3.8 ns
• Fully synchronous operation
• Pipelined mode
• Common data inputs and data outputs
• Asynchronous output enable control
• Available in 100-pin TQFP packages
• Byte write enables
• Clock enable for operation hold
• Multiple chip enables for easy expansion
• 2.5V core power supply
• Self-timed write cycles
• Interleaved or linear burst modes
• Snooze mode for standby operation
Logic block diagram
21
A[20:0]
CE0
CE1
CE2
R/W
BWa
BWb
ADV / LD
LBO
ZZ
D
Q
Address
register
Burst logic
CLK
Control
logic
CLK
DQ[a,b]
18
D ^Data
Input
Q
Register
CLK
CLK
CEN
21
D
Q
Write delay
addr. registers
21
CLK
CLK
2 M x 18
SRAM
Array
18
18
18
18
CLK
Output
Register
OE
18
OE
DQ[a,b]
Selection guide
Minimum cycle time
Maximum clock frequency
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
-200
-166
-133
Units
5
6
7.5
ns
200
166
133
MHz
3.2
3.5
3.8
ns
450
400
350
mA
170
150
140
mA
90
90
90
mA
1/17/05, V 1.2
Alliance Semiconductor
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