AS7C252MFT18A Datasheet, PDF (1/19 Pages) Alliance Semiconductor Corporation – 2.5V 2M x 18 Flow-through synchronous SRAM

January 2005
AS7C252MFT18A
®
2.5V 2M × 18 Flow-through synchronous SRAM
Features
• Organization: 2,097152 words × 18 bits
• Fast clock to data access: 7.5/8.5/10 ns
• Fast OE access time: 3.5/4.0 ns
• Fully synchronous flow-through operation
• Asynchronous output enable control
• Available in 100-pin TQFP package
• Individual byte write and global write
• Multiple chip enables for easy expansion
• 2.5V core power supply
• Linear or interleaved burst control
• Snooze mode for reduced power-standby
• Common data inputs and data outputs
Logic block diagram
CLK
ADV
ADSC
ADSP
A[20:0]
GWE
BW_b
BWE
BW_a
CE0
CE1
CE2
ZZ
OE
21
Power
down
LBO
CLK
CS
Burst logic
CLR
D
Q ²¹
CS
Address
register
CLK
19 21
2M x 18
Memory
array
18
18
D _DQb Q
Byte Write
registers
CLK
D _DQa Q
Byte Write
registers
CLK
D _Enable Q
register
CE
CLK
D _Enable Q
delay
register
CLK
2
OE
Output
registers
CLK
Input
registers
CLK
18
DQ[a,b]
Selection guide
Minimum cycle time
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
-75
-85
-10
Units
8.5
10
12
ns
7.5
8.5
10
ns
325
300
275
mA
130
130
130
mA
90
90
90
mA
1/17/05, v 1.2
Alliance Semiconductor
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