AS7C251MPFD32A Datasheet, PDF (1/19 Pages) Alliance Semiconductor Corporation – 2.5V 1M x 32/36 pipelined burst synchronous SRAM

February 2005
AS7C251MPFD32A
AS7C251MPFD36A
®
2.5V 1M × 32/36 pipelined burst synchronous SRAM
Features
• Organization: 1,048,576 words × 32 or 36 bits
• Fast clock speeds to 200 MHz
• Fast clock to data access: 3.1/3.5/3.8 ns
• Fast OE access time: 3.1/3.5/3.8 ns
• Fully synchronous register-to-register operation
• Double-cycle deselect
• Asynchronous output enable control
• Available in 100-pin TQFP package
• Individual byte write and global write
• Multiple chip enables for easy expansion
• 2.5V core power supply
• Linear or interleaved burst control
• Snooze mode for reduced power-standby
• Common data inputs and data outputs
Logic block diagram
CLK
ADV
ADSC
ADSP
A[19:0]
20
GWE
BWE
BW_d
BW_c
BW_b
BW_a
CE0
CE1
CE2
Selection guide
ZZ
Power
down
OE
Minimum cycle time
Maximum clock frequency
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
LBO
CLK
CE
CLR
Q0
Burst logic
Q1
D
Q
2
CE
Address
register
20 18
CLK
D _DQd Q
Byte write
registers
CLK
D _DQc Q
Byte write
registers
CLK
D _DQb Q
Byte write
registers
CLK
D _DQa Q
Byte write
registers
CLK
D
Q
Enable
CE register
CLK
D _Enable Q
delay
register
CLK
1M × 32/36
Memory
2
array
20
32/36
32/36
4
OE
Output
registers
CLK
Input
registers
CLK
32/36
DQ[a:d]
-200
-166
5
6
200
166
3.1
3.5
450
400
170
150
90
90
-133
7.5
133
3.8
350
140
90
Units
ns
MHz
ns
mA
mA
mA
2/11/05, v.1.1
Alliance Semiconductor
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