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AS7C251MPFD18A Datasheet, PDF (1/19 Pages) Alliance Semiconductor Corporation – 2.5V 1M x 18 pipelined burst synchronous SRAM | |||
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February 2005
AS7C251MPFD18A
®
2.5V 1M x 18 pipelined burst synchronous SRAM
Features
⢠Organization: 1,048,576 x18 bits
⢠Fast clock speeds to 166 MHz
⢠Fast clock to data access: 3.5/3.8 ns
⢠Fast OE access time: 3.5/3.8 ns
⢠Fully synchronous register-to-register operation
⢠Double-cycle deselect
⢠Asynchronous output enable control
⢠Available 100-pin TQFP package
⢠Individual byte write and global write
⢠Multiple chip enables for easy expansion
⢠2.5V core power supply
⢠Linear or interleaved burst control
⢠Snooze mode for reduced power-standby
⢠Common data inputs and data outputs
Logic block diagram
CLK
ADV
ADSC
ADSP
A[19:0]
GWE
BWb
BWE
BWa
CE0
CE1
CE2
ZZ
OE
20
Power
down
LBO
CLK
CS Burst logic
CLR
20
D
Q
CS
Address
register
CLK
18 20
1M x 18
Memory
array
18
18
D DQb Q
Byte Write
registers
CLK
D DQa Q
Byte Write
registers
CLK
D Enable Q
register
CE
CLK
D Enable Q
delay
register
CLK
2
OE
Output
registers
CLK
Input
registers
CLK
18
DQ[a,b]
Selection guide
Minimum cycle time
Maximum clock frequency
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
-166
-133
Units
6
7.5
ns
166
133
MHz
3.5
3.8
ns
290
270
mA
85
75
mA
40
40
mA
2/10/05, v. 1.2
Alliance Semiconductor
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