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AS7C251MNTD32A Datasheet, PDF (1/18 Pages) Alliance Semiconductor Corporation – 2.5V 1M x 32/36 Pipelined SRAM with NTD | |||
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January 2005
AS7C251MNTD32A
AS7C251MNTD36A
®
2.5V 1M Ã 32/36 Pipelined SRAM with NTDTM
Features
⢠Organization: 1,048,576 words à 32 or 36 bits
⢠NTDâ¢architecture for efficient bus operation
⢠Fast clock speeds to 200 MHz
⢠Fast clock to data access: 3.2/3.5/3.8 ns
⢠Fast OE access time: 3.2/3.5/3.8 ns
⢠Fully synchronous operation
⢠pipelined mode
⢠Common data inputs and data outputs
⢠Asynchronous output enable control
⢠Available in 100-pin TQFP packages
⢠Byte write enables
⢠Clock enable for operation hold
⢠Multiple chip enables for easy expansion
⢠2.5V core power supply
⢠Self-timed write cycles
⢠Interleaved or linear burst modes
⢠Snooze mode for standby operation
Logic block diagram
20
A[19:0]
CE0
CE1
CE2
R/W
BWa
BWb
BWc
BWd
ADV / LD
LBO
ZZ
D
Q
Address
register
Burst logic
CLK
Control
logic
CLK
DQ[a,b,c,d] 32/36
D Data
Input
Q
Register
CLK
20
D
Q
Write delay
addr. registers
20
CLK
CLK
32/36
1M x 32/36
SRAM
Array
32/36 32/36
CLK
CEN
Selection guide
Minimum cycle time
Maximum clock frequency
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
OE
-200
5
200
3.2
450
170
90
32/36
CLK
Output
Register
OE
32/36
DQ[a,b,c,d]
-166
-133
6
7.5
166
133
3.5
3.8
400
350
150
140
90
90
Units
ns
MHz
ns
mA
mA
mA
1/17/05, V 1.2
Alliance Semiconductor
P. 1 of 18
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