AS7C251MFT18A Datasheet, PDF (1/19 Pages) Alliance Semiconductor Corporation – 2.5V 1M x 18 flowthrough burst synchronous SRAM

December 2004
AS7C251MFT18A
®
2.5V 1M x 18 flowthrough burst synchronous SRAM
Features
• Organization: 1,048,576 words x18 bits
• Fast clock to data access: 7.5/8.5/10 ns
• Fast OE access time: 3.5/4.0 ns
• Fully synchronous flow-through operation
• Asynchronous output enable control
• Available 100-pin TQFP package
• Individual byte write and global write
• Multiple chip enables for easy expansion
• 2.5V core power supply
• Linear or interleaved burst control
• Snooze mode for reduced power-standby
Logic block diagram
CLK
ADV
ADSC
ADSP
A[19:0]
GWE
BW_b
BWE
BW_a
CE0
CE1
CE2
ZZ
OE
20
Power
down
LBO
CLK
CS _{Burst logic}
CLR
20
D
Q
CS
Address
register
CLK
18 20
1M x 18
Memory
array
18
18
D _DQb Q
Byte Write
registers
CLK
D _DQa Q
Byte Write
registers
CLK
D _Enable Q
register
CE
CLK
D _Enable Q
delay
register
CLK
2
OE
Output
buffers
Input
registers
CLK
18
DQ[a,b]
Selection guide
-75
-85
-10
Minimum cycle time
8.5
10
12
Maximum clock access time
7.5
8.5
10
Maximum operating current
275
250
230
Maximum standby current
90
80
80
Maximum CMOS standby current (DC)
60
60
60
Units
ns
ns
mA
mA
mA
12/24/04, v. 1.2
Alliance Semiconductor
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