AS7C1029 Datasheet, PDF (1/9 Pages) Alliance Semiconductor Corporation – 5V 256K X 4 CMOS SRAM (Center power and ground)

September 2006
Advance Information
®
5V 256K X 4 CMOS SRAM (Center power and ground)
Features
• Industrial (-40^o to 85^oC) temperature.
• Organization: 262,144 x 4 bits
• High speed
- 12 ns address access time
- 6 ns output enable access time
• Low power consumption via chip deselect
• Easy memory expansion with CE, OE inputs
• Center power and ground
• TTL/LVTTL-compatible, three-state I/O
• JEDEC-standard package
- 32-pin, 400 mil SOJ
• ESD protection ≥ 2000 volts
Pin arrangement
AS7C1029
Logic block diagram
V_CC
GND
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
Input buffer
I/O3
262,144 x 4
Array
(262,144)
I/O0
Address decoder
WE
Control
OE
circuit
CE
AAA AA AAA
10 11 12 13 14 15 16 17
32-pin SOJ (400 mil)
NC
1
A0
2
A1
3
A2
4
A3
5
CE
6
I/O0
7
V_CC
8
GND
9
I/O1
10
WE
11
A4
12
A5
13
A6
14
A7
15
NC
16
32 ^A17
31 A16
30 A15
29 ^A14
28 ^A13
27 OE
26 I/O3
25 GND
24
V_CC
23 I/O2
22 A12
21 A11
20 A10
19 A9
18 A8
17 NC
12/5/06, v. 1.0
Alliance Memory
P. 1 of 9
Copyright © Alliance Memory. All rights reserved.