AS7C1028 Datasheet, PDF (1/8 Pages) Alliance Semiconductor Corporation – 5V 256K X 4 CMOS SRAM (Common I/O)

September 2006
Advance Information
AS7C1028
®
5V 256K X 4 CMOS SRAM (Common I/O)
Features
• Industrial (-40^o to 85^oC) temperature
• Organization: 262,144 words × 4 bits
• High speed
- 12 ns address access time
- 6 ns output enable access time
• Low power consumption via chip deselect
• One chip select plus one Output Enable pin
• Bidirectional data inputs and outputs
• TTL-compatible
• 28-pin JEDEC standard packages
- 400 mil SOJ
• ESD protection ≥ 2000 volts
Logic block diagram
V_CC
GND
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
Input buffer
262,144 x 4
Array
(262,144)
Address decoder
AAA AA AAA
10 11 12 13 14 15 16 17
Control
circuit
Pin arrangement
28 Pin SOJ (400 mil)
I/O3
A0
1
A1
2
A2
3
A3
4
A4
5
A5
6
A6
7
A7
8
A8
9
A9
10
A10
11
CE
12
OE
13
GND
14
28
V_CC
27
A17
26
A16
25
A15
24
A14
23
A13
22
A12
21
A11
20
NC
19
I/O3
18
I/O2
17
I/O1
16
I/O0
15
WE
I/O0
WE
OE
CE
12/5/06; V.1.0
Alliance Memory
P. 1 of 8
Copyright © Alliance Memory. All rights reserved.