AS7C1026C Datasheet, PDF (1/9 Pages) Alliance Semiconductor Corporation – 5 V 64K X 16 CMOS SRAM

September 2006
Advance Information
AS7C1026C
®
5 V 64K X 16 CMOS SRAM
Features
• Industrial (-40^o to 85^oC) temperature
• Organization: 65,536 words × 16 bits
• Center power and ground pins for low noise
• High speed
- 12 ns address access time
- 6 ns output enable access time
• Low power consumption via chip deselect
• Easy memory expansion with CE, OE inputs
• TTL-compatible, three-state I/O
• Upper and Lower byte pin
• JEDEC standard packaging
- 44-pin 400 mil SOJ
- 44-pin TSOP 2-400
• ESD protection ≥ 2000 volts
Pin arrangement
44-Pin SOJ (400 mil), TSOP 2
Logic block diagram
A0
A1
A2
A3
A4
A5
A6
A7
I/O0–I/O7
I/O8–I/O15
I/O
buffer
WE
V_CC
65,536 x 16
GND
Array
Control circuit
Address decoder
A4
1
A3
2
A2
3
A1
4
A0
5
CE
6
I/O0
7
I/O1
8
I/O2
9
I/O3
10
V_CC
11
GND
12
I/O4
13
I/O5
14
I/O6
15
I/O7
16
WE
17
A15
18
A14
19
A13
20
A12
21
NC
22
44
A5
43
A6
42
A7
41
OE
40
UB
39
LB
38
I/O15
37
I/O14
36
I/O13
35
I/O12
34
GND
33
V_CC
32
I/O11
31
I/O10
30
I/O9
29
I/O8
28
NC
27
A8
26
A9
25
A10
24
A11
23
NC
UB
OE
LB
CE
12/5/06, v 1.0
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