AS7C1026B Datasheet, PDF (1/10 Pages) Alliance Semiconductor Corporation – 5 V 64K X 16 CMOS SRAM

March 2004
AS7C1026B
®
5 V 64K X 16 CMOS SRAM
Features
• Industrial and commercial versions
• Organization: 65,536 words × 16 bits
• Center power and ground pins for low noise
• High speed
- 10/12/15/20 ns address access time
- 5, 6, 7, 8 ns output enable access time
• Low power consumption: ACTIVE
- 605 mW / max @ 10 ns
• Low power consumption: STANDBY
- 55 mW / max CMOS I/O
• 6 T 0.18 u CMOS technology
• Easy memory expansion with CE, OE inputs
Logic block diagram
A0
A1
A2
A3
A4
A5
A6
A7
I/O0–I/O7
I/O8–I/O15
I/O
buffer
V_CC
64 K × 16
GND
Array
Control circuit
WE
Column decoder
• TTL-compatible, three-state I/O
• JEDEC standard packaging
- 44-pin 400 mil SOJ
- 44-pin TSOP 2-400
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
Pin arrangement
44-Pin SOJ (400 mil), TSOP 2
A4
1
A3
2
A2
3
A1
4
A0
5
CE
6
I/O0
7
I/O1
8
I/O2
9
I/O3
10
V_CC
11
GND
12
I/O4
13
I/O5
14
I/O6
15
I/O7
16
WE
17
A15
18
A14
19
A13
20
A12
21
NC
22
44
A5
43
A6
42
A7
41
OE
40
UB
39
LB
38
I/O15
37
I/O14
36
I/O13
35
I/O12
34
GND
33
V_CC
32
I/O11
31
I/O10
30
I/O9
29
I/O8
28
NC
27
A8
26
A9
25
A10
24
A11
23
NC
UB
OE
LB
CE
Selection guide
Maximum address access time
Maximum output enable access time
Maximum operating current
Maximum CMOS standby current
-10
-12
-15
-20
Unit
10
12
15
20
ns
5
6
7
8
ns
110
100
90
80
mA
10
10
10
10
mA
3/26/04, v 1.3
Alliance Semiconductor
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