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AS7C1026 Datasheet, PDF (1/10 Pages) Alliance Semiconductor Corporation – 5V / 3.3V 64KX16 CMOS SRAM
March 2001
AS7C1026
AS7C31026
®
5V/3.3V 64K×16 CMOS SRAM
Features
• AS7C1026 (5V version)
• AS7C31026 (3.3V version)
• Industrial and commercial versions
• Organization: 65,536 words x 16 bits
• Center power and ground pins for low noise
• High speed
- 12/15/20 ns address access time
- 6,7,8 ns output enable access time
• Low power consumption: ACTIVE
- 880 mW (AS7C1026) / max @ 12 ns
- 396 mW (AS7C31026) / max @ 12 ns
• Low power consumption: STANDBY
- 28 mW (AS7C1026) / max CMOS I/O
- 18 mW (AS7C31026) / max CMOS I/O
• 2.0V data retention
• Easy memory expansion with CE, OE inputs
• TTL-compatible, three-state I/O
• JEDEC standard packaging
- 44-pin 400 mil SOJ
- 44-pin 400 mil TSOP II
- 48-ball 6 mm × 8 mm CSP mBGA
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
Logic block diagram
A0
A1
A2
A3
A4
A5
A6
A7
I/O0–I/O7
I/O8–I/O15
I/O
buffer
WE
UB
OE
LB
CE
64K × 16
Array
Control circuit
Column decoder
Pin arrangement
44-Pin SOJ, TSOP II (400 mil)
VCC
A4 1
GND
A3 2
A2 3
A1 4
A0 5
CE 6
I/O0 7
I/O1 8
I/O2 9
I/O3 10
VCC
11
GND 12
I/O4 13
I/O5 14
I/O6 15
I/O7 16
WE 17
A15 18
A14 19
A13 20
A12 21
NC 22
44 A5
43 A6
42 A7 48-CSP mini Ball-Grid-Array Package
41 OE
40 UB
1 2 3 45 6
39 LB
38 I/O15 A LB OE A0 A1 A2 NC
37 I/O14
36 I/O13 B I/O8 UB A3 A4 CE I/O0
35 I/O12
34 GND C I/O9 I/O10 A5 A6 I/O1 I/O2
33
32
VCC
I/O11
D
VSS I/O11 NC
A7 I/O3 VDD
31
30
I/O10
I/O9
E
VDD I/O12 NC
NC I/O4 VSS
29
28
I/O8
NC
F I/O14 I/O13 A14 A15 I/O5 I/O6
27 A8
26 A9
G I/O15 NC A12 A13 WE I/O7
25
24
A10
A11
H NC
A8
A9 A10 A11 NC
23 NC
Selection guide
Maximum address access time
Maximum output enable access time
Maximum operating current
Maximum CMOS standby current
Shaded areas indicate preliminary information.
AS7C1026
AS7C31026
AS7C1026
AS7C31026
AS7C1026-12 AS7C1026-15 AS7C1026-20
AS7C31026-12 AS7C31026-15 AS7C31026-20 Unit
12
15
20
ns
6
8
10
ns
160
150
140
mA
110
100
90
mA
10
10
15
mA
10
10
15
mA
3/23/01; v.1.0
Alliance Semiconductor
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