AS7C1025B Datasheet, PDF (1/9 Pages) Alliance Semiconductor Corporation – 5V 128K X 8 CMOS SRAM (Center power and ground)

March 2004
AS7C1025B
®
5V 128K X 8 CMOS SRAM (Center power and ground)
Features
• Industrial and commercial temperatures
• Organization: 131,072 x 8 bits
• High speed
- 10/12/15/20 ns address access time
- 5/6/7/8 ns output enable access time
• Low power consumption: ACTIVE
- 605mW / max @ 10 ns
• Low power consumption: STANDBY
- 55 mW / max CMOS
• 6 T 0.18 u CMOS technology
• Easy memory expansion with CE, OE inputs
• Center power and ground
• TTL/LVTTL-compatible, three-state I/O
Logic block diagram
V_CC
GND
A0
A1
A2
A3
A4
A5
A6
A7
A8
Input buffer
I/O7
512 x 256 x 8
Array
(1,048,576)
I/O0
Column decoder
Control
circuit
WE
OE
CE
• JEDEC-standard packages
- 32-pin, 300 mil SOJ
- 32-pin, 400 mil SOJ
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
Pin arrangement
32-pin SOJ (300 mil)
32-pin SOJ (400 mil)
A0
1
A1
2
A2
3
A3
4
CE
5
I/O0
6
I/O1
7
V_CC
8
GND
9
I/O2
10
I/O3
11
WE
12
A4
13
A5
14
A6
15
A7
16
32 ^A16
31 A15
30 A14
29 A13
28 OE
27 I/O7
26 I/O6
25 GND
24
V_CC
23 I/O5
22 I/O4
21 A12
20 A11
19 A10
18 A9
17 A8
Selection guide
-10
Maximum address access time
10
Maximum output enable access time
5
Maximum operating current
110
Maximum CMOS standby current
10
-12
-15
12
15
6
7
100
90
10
10
-20
Unit
20
ns
8
ns
80
mA
10
mA
3/26/04, v. 1.3
Alliance Semiconductor
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