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AS7C1025A Datasheet, PDF (1/8 Pages) Alliance Semiconductor Corporation – 5V/3.3V 128K X 8 CMOS SRAM (Revolutionary pinout)
January 2001
Advance Information
AS7C1025A
AS7C31025A
®
5V/3.3V 128K X 8 CMOS SRAM (Revolutionary pinout)
Features
• AS7C1025A (5V version)
• AS7C31025A (3.3V version)
• Industrial and commercial temperatures
• Organization: 131,072 x 8 bits
• High speed
- 10/10/12/15/20 ns address access time
- 3/3/4/5 ns output enable access time
• Low power consumption: ACTIVE
- 660 mW (AS7C1025A) / max @ 10 ns (5V)
- 324 mW (AS7C31025A) / max @ 10 ns (3.3V)
• Low power consumption: STANDBY
- 55 mW (AS7C1025A) / max CMOS (5V)
- 36 mW (AS7C31025A) / max CMOS (3.3V)
Logic block diagram
VCC
GND
Input buffer
A0
A1
I/O7
A2
A3
512×256×8
A4
Array
A5
(1,048,576)
A6
A7
I/O0
A8
WE
Column decoder
Control
circuit
OE
CE
• Latest 6T 0.25u CMOS technology
• 2.0V data retention
• Easy memory expansion with CE, OE inputs
• Center power and ground
• TTL/LVTTL-compatible, three-state I/O
• JEDEC-standard packages
- 32-pin, 300 mil SOJ
- 32-pin, 400 mil SOJ
- 32-pin, TSOP II
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
Pin arrangement
32-pin TSOP II
A0 1
A1 2
A2 3
A3 4
CE 5
I/O0 6
I/O1 7
VCC 8
GND 9
I/O2 10
I/O3 11
WE 12
A4 13
A5 14
A6 15
A7 16
32 A16
31 A15
30 A14
29 A13
28 OE
27 I/O7
26 I/O6
25 GND
24 VCC
23 I/O5
22 I/O4
21 A12
20 A11
19 A10
18 A9
17 A8
32-pin SOJ (300 mil)
32-pin SOJ (400 mil)
A0
1
A1
2
A2
3
A3
4
CE
5
I/O0
6
I/O1
7
VCC
8
GND
9
I/O2
10
I/O3
11
WE
12
A4
13
A5
14
A6
15
A7
16
32 A16
31 A15
30 A14
29 A13
28 OE
27 I/O7
26 I/O6
25 GND
24
VCC
23 I/O5
22 I/O4
21 A12
20 A11
19 A10
18 A9
17 A8
Selection guide
Maximum address access time
AS7C1025A-10
AS7C31025A-10
10
AS7C1025A-12
AS7C31025A-12
12
AS7C1025A-15
AS7C31025A-15
15
AS7C1025A-20
AS7C31025A-20
20
Maximum output enable access
time
3
3
4
5
Maximum
AS7C1025A
120
110
100
100
operating
current
AS7C31025A
90
80
80
80
Maximum
AS7C1025A
10
10
10
15
CMOS standby
current
AS7C31025A
10
10
10
15
Unit
ns
ns
mA
mA
mA
mA
2/6/01; V.0.9
Alliance Semiconductor
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