AS7C1025 Datasheet, PDF (1/9 Pages) Alliance Semiconductor Corporation – 5V/3.3V 128K x8 CMOS SRAM (Revolutionary pinout)

March 2001
AS7C1025
AS7C31025
®
5V/3.3V 128Kx8 CMOS SRAM (Revolutionary pinout)
Features
• AS7C1025 (5V version)
• AS7C31025 (3.3V version)
• Industrial and commercial temperatures
• Organization: 131,072 words × 8 bits
• High speed
- 12/15/20 ns address access time
- 6,7,8 ns output enable access time
• Low power consumption: ACTIVE
- 715 mW (AS7C1025) / max @ 12 ns (5V)
- 360 mW (AS7C31025) / max @ 12 ns (3.3V)
• Low power consumption: STANDBY
- 27.5 mW (AS7C1025) / max CMOS (5V)
- 1.8 mW (AS7C31025) / max CMOS (3.3V)
• 2.0V data retention
• Easy memory expansion with CE, OE inputs
• Center power and ground
• TTL/LVTTL-compatible, three-state I/O
• JEDEC-standard packages
- 32-pin, 300 mil SOJ
- 32-pin, 400 mil SOJ
- 32-pin TSOP II
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
Logic block diagram
Pin arrangement
V_CC
GND
Input buffer
A0
A1
A2
A3
A4
512×256×8
Array
A5
(1,048,576)
A6
A7
A8
I/O7
I/O0
32-pin TSOP II
A0 1
A1 2
A2 3
A3 4
CE 5
I/O0 6
I/O1 7
V_CC 8
GND 9
I/O2 10
I/O3 11
WE 12
A4 13
A5 14
A6 15
A7 16
32 A16
31 _A15
30 _A14
29 _A13
28 _OE
27 _I/O7
26 _I/O6
25 _GND
24 _VCC
23 _I/O5
22 _I/O4
21 _A12
20 _A11
19 _A10
18 A9
17 A8
WE
Column decoder
Control
circuit
OE
CE
32-pin SOJ (300 mil)
32-pin SOJ (400 mil)
A0
1
A1
2
A2
3
A3
4
CE
5
I/O0
6
I/O1
7
V_CC
8
GND
9
I/O2
10
I/O3
11
WE
12
A4
13
A5
14
A6
15
A7
16
32 ^A16
31 A15
30 A14
29 A13
28 OE
27 I/O7
26 I/O6
25 GND
24
V_CC
23 I/O5
22 I/O4
21 A12
20 A11
19 A10
18 A9
17 A8
Selection guide
Maximum address access time
Maximum output enable access time
Maximum operating current
AS7C1025
AS7C31025
AS7C1025
Maximum CMOS standby current
AS7C31025
AS7C1025-12
AS7C31025-12
12
3
130
100
5
5
AS7C1025-15
AS7C31025-15
15
4
85
85
5
5
AS7C1025-20
AS7C31025-20 Unit
20
ns
5
ns
80
mA
80
mA
5
mA
5
mA
Shaded areas contain advance information.
3/23/01; v.1.0
Alliance Semiconductor
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