AS7C1024C Datasheet, PDF (1/9 Pages) Alliance Semiconductor Corporation – 5V 128K X 8 CMOS SRAM

September 2006
Advance Information
AS7C1024C
®
5V 128K X 8 CMOS SRAM
Features
• Industrial (-40^o to 85^oC) temperature
• Organization: 131,072 x 8 bits
• High speed
- 12 ns address access time
- 6 ns output enable access time
• Low power consumption via chip deselect
• Easy memory expansion with CE1, CE2, OE inputs
• TTL/LVTTL-compatible, three-state I/O
• 32-pin JEDEC standard packages
- 300 mil SOJ
- 400 mil SOJ
• ESD protection ≥ 2000 volts
Pin arrangement
Logic block diagram
V_CC
GND
Input buffer
A0
A1
A2
A3
131,702 x 8
A4
Array
A5
A6
(1,048,576)
A7
A8
Address decoder
Control
circuit
I/O7
I/O0
WE
OE
CE1
CE2
32-pin SOJ (300 mil)
32-pin SOJ (400 mil)
NC
1
A16
2
A14
3
A12
4
A7
5
A6
6
A5
7
A4
8
A3
9
A2
10
A1
11
A0
12
I/O0
13
I/O1
14
I/O2
15
GND
16
32
V_CC
31 A15
30 CE2
29 WE
28 A13
27 A8
26 A9
25 ^A11
24 OE
23 A10
22 CE1
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3
12/5/06, v. 1.0
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