AS7C1024A Datasheet, PDF (1/9 Pages) Alliance Semiconductor Corporation – 5V/3.3V 128KX8 CMOS SRAM (Evolutionary Pinout)

May 2002
®
5V/3.3V 128KX8 CMOS SRAM (Evolutionary Pinout)
AS7C1024A
AS7C31024A
Features
• AS7C1024A (5V version)
• AS7C31024A (3.3V version)
• Industrial and commercial temperatures
• Organization: 131,072 words x 8 bits
• High speed
- 10/12/15/20 ns address access time
- 5, 6, 7, 8 ns output enable access time
• Low power consumption: ACTIVE
- 853 mW (AS7C1024A) / max @ 10 ns
- 522 mW (AS7C31024A) / max @ 10 ns
• Low power consumption: STANDBY
- 55 mW (AS7C1024A) / max CMOS
- 36 mW (AS7C31024A) / max CMOS
Logic block diagram
V_CC
GND
Input buffer
A0
A1
A2
A3
512×256×8
A4
Array
A5
A6
(1,048,576)
A7
A8
Column decoder
Control
circuit
• Latest 6T 0.25u CMOS technology
• Easy memory expansion with CE1, CE2, OE inputs
• TTL/LVTTL-compatible, three-state I/O
• 32-pin JEDEC standard packages
- 300 mil SOJ
- 400 mil SOJ
- 8 × 20mm TSOP 1
- 8 x 13.4mm sTSOP 1
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
Pin arrangement
32-pin SOJ (300 mil)
32-pin SOJ (400 mil)
I/O7
NC
1
A16
2
A14
3
A12
4
A7
5
A6
6
A5
7
A4
8
A3
9
A2
10
A1
11
A0
12
I/O0
13
I/O1
14
I/O2
15
GND
16
32
V_CC
31 A15
30 CE2
29 _WE
28 _A13
27 _A8
26 A9
25 ^A11
24 OE
23 A10
22 _CE1
21 _I/O7
20 _I/O6
19 _I/O5
18 _I/O4
17 _I/O3
32-pin (8 x 20mm) TSOP I
32-pin (8 x 13.4mm) sTSOP1
I/O0
WE
OE
CE1
CE2
A11 1
A9 2
A8 3
A13 4
WE 5
CE2 6
A15 7
V_CC
NC
A16
8
9
10
A14 ¹¹
A12 ¹²
A7
13
A6
14
A5 ¹⁵
A4 ¹⁶
32 OE
31 A10
30 CE1
29 I/O7
28 I/O6
27 I/O5
26 I/O4
25 I/O3
24 GND
23 I/O2
22 I/O1
21 _I/O0
20
A0
19
A1
18
A2
17
A3
Selection guide
-10
-12
-15
-20
Unit
Maximum address access time
10
12
15
20
ns
Maximum output enable access time
5
6
7
8
ns
Maximum
AS7C1024A
155
150
145
140
mA
operating current _AS7C31024A
145
140
135
130
mA
Maximum CMOS ^AS7C1024A
10
10
10
10
mA
standby current _AS7C31024A
5
5
5
5
mA
9/26/02; 0.9.9
Alliance Semiconductor
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