AS6VA25616 Datasheet, PDF (1/9 Pages) Alliance Semiconductor Corporation – 2.7V to 3.3V 256K x 16 Intelliwatt low-power CMOS SRAM with one chip enable

October 2000
AS6VA25616
®
2.7V to 3.3V 256K × 16 Intelliwatt™ low-power CMOS SRAM with one chip enable
Features
• AS6VA25616
• Intelliwatt™ active power circuitry
• Industrial and commercial temperature ranges available
• Organization: 262,144 words × 16 bits
• 2.7V to 3.3V at 55 ns
• Low power consumption: ACTIVE
- 132 mW at 3.3V and 55 ns
• Low power consumption: STANDBY
- 66 µW max at 3.3V
Logic block diagram
A0
A1
A2
A3
A4
A6
A7
A8
A12
A13
I/O1–I/O8
I/O9–I/O16
I/O
buffer
V_CC
256K × 16
V_SS
Array
(4,194,304)
Control circuit
WE
Column decoder
UB
OE
LB
CS
• 1.2V data retention
• Equal access and cycle times
• Easy memory expansion with CS, OE inputs
• Smallest footprint packages
- 48-ball FBGA
- 400-mil 44-pin TSOP II
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
Pin arrangement (top view)
44-pin 400-mil TSOP II
A4 1 44
A3 2 43
A2 3 42
A1 4 41
A0 5 40
CS 6 39
I/O1
7
38
I/O2
8
37
I/O3
9
36
I/O4
10 35
I/VOV^C5^SCS
11
12
13
34
33
32
I/O6
14 31
I/O7
15 30
I/O8
16 29
WE 17 28
A17 18 27
A16 19 26
A15 20 25
A14 21 24
A13 22 23
A5
A6
A7
OE
UB
LB
I/O16
I/O15
I/O14
I/O13
VVI/O_SCSC12
I/O11
I/O10
I/O9
NC
A8
A9
A10
A11
A12
48-CSP Ball-Grid-Array Package
123456
A LB OE A0 A1 A2 NC
B I/O9 UB A3 A4 CS I/O1
C I/O10 I/O11 A5 A6 I/O2 I/O3
D V_SS I/O12 A17 A7 I/O4 V_CC
E V_CC I/O13 NC A16 I/O5 V_SS
F I/O15 I/O14 A14 A15 I/O6 I/O7
G I/O16 NC A12 A13 WE I/O8
H NC A8 A9 A10 A11 NC
Selection guide
V_CC Range
Min
Typ²
Max
Product
(V)
(V)
(V)
AS6VA25616
2.7
3.0
3.3
Speed
(ns)
55
Power Dissipation
Operating (I_CC)
Max (mA)
Standby (I_SB1)
Max (µA)
2
20
10/6/00
ALLIANCE SEMICONDUCTOR
1
Copyright ©2000 Alliance Semiconductor. All rights reserved.