AS6UA51216 Datasheet, PDF (1/9 Pages) Alliance Semiconductor Corporation – 1.65V to 3.6V 512K×16 Intelliwatt low power CMOS SRAM with one chip enable

Advance Information
June 2000
AS6UA51216
1.65V to 3.6V 512K×16 Intelliwatt™ low power CMOS SRAM with one chip enable
Features
• AS6UA51216
• Intelliwatt™ active power circuitry
• Industrial and commercial temperature ranges available
• Organization: 524,288 words × 16 bits
• 2.7V to 3.6V at 55 ns
• 2.3V to 2.7V at 70 ns
• 1.65V to 2.3V at 100 ns
• Low power consumption: ACTIVE
- 144 mW at 3.6V and 55 ns
- 68 mW at 2.7V and 70 ns
- 28 mW at 2.3 V and 100 ns
Logic block diagram
A0
A1
A2
A3
A4
A6
A7
A8
A12
A13
I/O1–I/O8
I/O9–I/O16
I/O
buffer
V_DD
512K × 16
V_SS
Array
(8,388,608)
Control circuit
WE
Column decoder
UB
OE
LB
CS
Selection guide
V_CC Range
Min
Typ²
Max
Product
(V)
(V)
(V)
AS6UA51216
2.7
3.0
3.6
AS6UA51216
2.3
2.5
2.7
AS6UA51216
1.65
2.0
2.3
• Low power consumption: STANDBY
- 72 µW max at 3.6V
- 41 µW max at 2.7V
- 28 µW max at 2.3V
• 1.2V data retention
• Equal access and cycle times
• Easy memory expansion with CS, OE inputs
• Smallest footprint packages
- 48-ball FBGA
- 400-mil 44-pin TSOP II
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
Pin arrangement (top view)
44-pin 400-mil TSOP II
A4
A3
A2
A1
A0
CS
I/O1
I/O2
I/O3
I/O4
V_CC
I/VO^S5^S
I/O6
I/O7
I/O8
WE
A18
A17
A16
A15
A14
1 44
2 43
3 42
4 41
5 40
6 39
7 38
8 37
9 36
10 35
11 34
12 33
13 32
14 31
15 30
16 29
17 28
18 27
19 26
20 25
21 24
22 23
A5
A6
A7
OE
UB
LB
I/O16
I/O15
I/O14
I/O13
VVI/_CSOSC12
I/O11
I/O10
I/O9
A8
A9
A10
A11
A12
A13
Note: A “MODE” pad is to be placed between pins 33 and 34 and 11 and 12,
shorted. The bonding of this pad to V_CC or V_SS configures the device. There should
only be 44+2+2 pads on the chip. Two extra V_CC to separate out Array from
Peripheral and Two-Mode Pads.
48-CSP Ball-Grid-Array Package
123456
A LB OE A0 A1 A2 NC
B I/O9 UB A3 A4 CS I/O1
C I/O10 I/O11 A5 A6 I/O2 I/O3
D V_SS I/O12 A17 A7 I/O4 V_CC
E V_CC I/O13 V_SS A16 I/O5 V_SS
F I/O15 I/O14 A14 A15 I/O6 I/O7
G I/O16 NC A12 A13 WE I/O8
H A18 A8 A9 A10 A11 NC
Speed
(ns)
55
70
100
Power Dissipation
Operating (I_CC1)
Max (mA)
Standby (I_SB2)
Max (µA)
2
20
1
15
1
12
6/27/00
ALLIANCE SEMICONDUCTOR
1
Copyright ©2000 Alliance Semiconductor. All rights reserved.