AS6C6264-55PCN Datasheet, PDF (1/12 Pages) Alliance Semiconductor Corporation – 8K X 8 BIT LOW POWER CMOS SRAM

February 2007
AS6C6264
®
8K X 8 BIT LOW POWER CMOS SRAM
FEATURES
GENERAL DESCRIPTION
Access time :55ns
Low power consumption:
Operation current :
15mA (TYP.), VCC = 3.0V
Standby current :
1µ A (TYP.), VCC = 3.0V
Wide range power supply : 2.7 ~ 5.5V
Fully Compatible with all Competitors 5V product
Fully Compatible with all Competitors 3.3V product
All inputs and outputs TTL compatible
Fully static operation
Tri-state output
Data retention voltage :1.5V (MIN.)
All products ROHS Compliant
Package : 28-pin 600 mil PDIP
28-pin 330 mil SOP
28-pin 8mm x 13.4mm sTSOP
The AS6C6264 is a 65,536-bit low power CMOS
static random access memory organized as 8,192
words by 8 bits. It is fabricated using very high
performance, high reliability CMOS technology. Its
standby current is stable within the range of
operating temperature.
The AS6C6264 is well designed for low power
application, and particularly well suited for battery
back-up nonvolatile memory application.
The AS6C6264 operates with wide range power
supply.
FUNCTIONAL BLOCK DIAGRAM
Vcc
Vss
A0-A12
DE CODE R
8K x8
ME MOR Y AR R AY
D Q 0- D Q 7
CE#
CE2
WE #
OE #
I/O DAT A
CIR CUIT
CONTR OL
CIR CUIT
C OLUM N I/O
PIN DESCRIPTION
SYMBOL
A0 - A12
DQ0 – DQ7
CE#, CE2
WE#
OE#
VCC
VSS
NC
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip Enable Inputs
Write Enable Input
Output Enable Input
Power Supply
Ground
No Connection
02/Feb/07, v1.0
Alliance Memory Inc
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