AS4LC4M4F1 Datasheet, PDF (1/14 Pages) Alliance Semiconductor Corporation – 4M×4 CMOS DRAM (Fast Page) 3.3V Family

May 2001
AS4LC4M4F1
®
4M×4 CMOS DRAM (Fast Page) 3.3V Family
Features
• Organization: 4,194,304 words × 4 bits
• High speed
- 50/60 ns RAS access time
- 25/30 ns column address access time
- 12/15 ns CAS access time
• Low power consumption
- Active: 500 mW max
- Standby: 3.6 mW max, CMOS I/O
• Fast page mode
• Refresh
- 2048 refresh cycles, 32 ms refresh interval
- RAS-only or CAS-before-RAS refresh or self-refresh
• TTL-compatible, three-state I/O
• JEDEC standard package
- 300 mil, 24/26-pin SOJ
• 3.3V power supply
• Latch-up current ≥ 200 mA
• ESD protection ≥ 2000 volts
• Industrial and commercial temperature available
Pin arrangement
SOJ
TSOP*
V_{CC 1}
I/O0 2
I/O1 3
WE 4
RAS 5
NC 6
26 ^GND
25 ^I/O3
24 ^I/O2
23 CAS
22 OE
21 A9
V_{CC 1}
I/O0 2
I/O1 3
WE 4
RAS 5
NC 6
19 ^GND
18 ^I/O3
17 ^I/O2
16 ^CAS
15 ^OE
14 A9
A10 8
A0 9
A1 10
A2 11
A3 ¹²
V_CC ¹³
19 ^A8
18 ^A7
17 A6
16 A5
15 A4
14 GND
A10 8
A0 ⁹
A1 ¹⁰
A2 ¹¹
A3 ¹²
V_CC ¹³
26 ^A8
25 ^A7
24 A6
23 A5
22 A4
21 GND
*TSOP availability to be determined
Pin designation
Pin(s)
Description
A0 to A10
Address inputs
RAS
Row address strobe
CAS
Column address strobe
WE
Write enable
I/O0 to I/O3
Input/output
OE
Output enable
V_CC
GND
Power
Ground
Selection guide
Maximum RAS access time
Maximum column address access time
Maximum CAS access time
Maximum output enable (OE) access time
Minimum read or write cycle time
Minimum fast page mode cycle time
Maximum operating current
Maximum CMOS standby current
Symbol
AS4LC4M4F1-50
AS4LC4M4F1-60
Unit
t_RAC
50
t_CAA
25
t_CAC
12
t_OEA
13
t_RC
80
t_PC
25
I_CC1
120
I_CC5
1.0
60
ns
30
ns
15
ns
15
ns
100
ns
30
ns
110
mA
1.0
mA
5/16/01; v.1.0 Restored
Alliance Semiconductor
P. 1 of 14
Copyright © Alliance Semiconductor. All rights reserved.