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AS4LC2M8S1 Datasheet, PDF (1/28 Pages) Alliance Semiconductor Corporation – 3.3V 2M x 8/1M x 16 CMOS synchronous DRAM
Advance information
AS4LC2M8S1
AS4LC1M16S1
3.3V 2M × 8/1M × 16 CMOS synchronous DRAM
Features
• Organization
• PC100 functionality
- 1,048,576 words × 8 bits × 2 banks (2M × 8)
• Automatic and direct precharge including concurrent
11 row, 9 column address
autoprecharge
- 524,288 words × 16 bits × 2 banks (1M × 16)
• Burst read, write/Single write
11 row,8 column address
• Random column address assertion in every cycle, pipelined
• All signals referenced to positive edge of clock, fully
operation
synchronous
• LVTTL compatible I/O
• Dual internal banks controlled by A11 (bank select)
• 3.3V power supply
• High speed
• JEDEC standard package, pinout and function
- 143/125/100 MHz
- 400 mil, 44-pin TSOP II (2M × 8)
- 7/8/10 ns clock access time
- 400 mil, 50-pin TSOP II (1M × 16)
• Low power consumption
• Read/write data masking
- Active: 576 mW max
- Standby: 7.2 mW max, CMOS I/O
• Programmable burst length (1/2/4/8/ full page)
• 2048 refresh cycles, 64 ms refresh interval
• Programmable burst sequence (sequential/interleaved)
• Auto refresh and self refresh (2K self refresh mode at 64 ms) • Programmable CAS latency (1/2/3)
Pin arrangement
VCC
DQ0
VSSQ
DQ1
VCCQ
DQ2
VSSQ
DQ3
VCCQ
NC
NC
WE
CAS
RAS
CS
A11
A10
A0
A1
A2
A3
VCC
TSOP II
1
44
2
43
3
42
4
41
5
40
6
39
7
38
8
37
9
36
10
35
11
34
12
33
13
32
14
31
15
30
16
29
17
28
18
27
19
26
20
25
21
24
22
23
VSS
DQ7
VSSQ
DQ6
VCCQ
DQ5
VSSQ
DQ4
VCCQ
NC
NC
DQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
VSS
VCC
DQ0
DQ1
VSSQ
DQ2
DQ3
VCCQ
DQ4
DQ5
VSSQ
DQ6
DQ7
VCCQ
LDQM
WE
CAS
RAS
CS
A11
A10
A0
A1
A2
A3
VCC
LEGEND
Configuration
Refresh Count
Row Address
Bank Address
Column Address
2M × 8
1M × 8 × 2 banks
2K
2K (A0 – A10)
2 (BA)
512 (A0 – A8)
TSOP II
1
50
2
49
3
48
4
47
5
46
6
45
7
44
8
43
9
42
10
41
11
40
12
39
13
38
14
37
15
36
16
35
17
34
18
33
19
32
20
31
21
30
22
29
23
28
24
27
25
26
VSS
DQ15
DQ14
VSSQ
DQ13
DQ12
VCCQ
DQ11
DQ10
VSSQ
DQ9
DQ8
VCCQ
NC
UDQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
VSS
1M × 16
512K × 16 × 2 banks
2K
2K (A0 – A10)
2 (BA)
256 (A0 – A7)
Pin designation
Pin(s)
DQM (2M × 8)
UDQM/LDQM (1M × 16)
A0 to A10
A11
DQ0 to DQ7 (2M × 8)
DQ0 to DQ15 (1M × 16)
RAS
CAS
WE
CS
VCC, VCCQ
VSS, VSSQ
CLK
CKE
Description
Output disable/write mask
RA0 – 10
Address inputs CA0 – 7 (×16)
CA0 – 8 (×8)
Bank address (BA)
Input/output
Row address strobe
Column address strobe
Write enable
Chip select
Power (3.3V ± 0.3V)
Ground
Clock input
Clock enable
Selection guide
Symbol
–7
–8
–10
Unit
Bus frequency (CL = 3)
fMax
143
125
100
MHz
Maximum clock access time (CL = 3)
tAC
5.5
6
6
ns
Minimum input setup time
tS
2
2
2
ns
Minimum input hold time
tH
1.0
1.0
1.0
ns
Row cycle time (CL = 3, BL = 1)
tRC
70
80
80
ns
Maximum operating current ([×16], RD or
WR, CL = 3), BL = 2
ICC1
130
100
100
mA
Maximum CMOS standby current, self refresh
ICC6
1
1
1
mA
7/5/00
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