AS4LC1M16S0 Datasheet, PDF (1/29 Pages) Alliance Semiconductor Corporation – 3.3V 2M × 8/1M × 16 CMOS synchronous DRAM

May 2001
Preliminary
AS4LC2M8S1
AS4LC2M8S0
®
AS4LC1M16S1
3.3V 2M × 8/1M × 16 CMOS synchronous DRAM
AS4LC1M16S0
Features
• Organization
- 1,048,576 words × 8 bits × 2 banks (2M × 8)
11 row, 9 column address
- 524,288 words × 16 bits × 2 banks (1M × 16)
11 row, 8 column address
• All signals referenced to positive edge of clock, fully
synchronous
• Dual internal banks controlled by A11 (bank select)
• High speed
- 143/125/100 MHz
- 7/8/10 ns clock access time
• Low power consumption
- Active: 576 mW max
- Standby: 7.2 mW max, CMOS I/O
• 2048 refresh cycles, 32 ms refresh interval
• 4096 refresh cycles, 64 ms refresh interval
• Auto refresh and self refresh
• PC100 functionality
• Automatic and direct precharge including concurrent
autoprecharge
• Burst read, write/Single write
• Random column address assertion in every cycle, pipelined
operation
• LVTTL compatible I/O
• 3.3V power supply
• JEDEC standard package, pinout and function
- 400 mil, 44-pin TSOP 2 (2M × 8)
- 400 mil, 50-pin TSOP 2 (1M × 16)
• Read/write data masking
• Programmable burst length (1/2/4/8/ full page)
• Programmable burst sequence (sequential/interleaved)
• Programmable CAS latency (1/2/3)
Pin arrangement
V_CC
DQ0
V_SSQ
DQ1
V_CCQ
DQ2
V_SSQ
DQ3
V_CCQ
NC
NC
WE
CAS
RAS
CS
A11
A10
A0
A1
A2
A3
V_CC
TSOP 2
1
44
2
43
3
42
4
41
5
40
6
39
7
38
8
37
9
36
10
35
11
34
12
33
13
32
14
31
15
30
16
29
17
28
18
27
19
26
20
25
21
24
22
23
LEGEND
Configuration
Refresh Count
Row Address
Bank Address
Column Address
Selection guide
V_SS
DQ7
V_SSQ
DQ6
V_CCQ
DQ5
V_SSQ
DQ4
V_CCQ
NC
NC
DQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
V_SS
V_CC
DQ0
DQ1
V_SSQ
DQ2
DQ3
V_CCQ
DQ4
DQ5
V_SSQ
DQ6
DQ7
V_CCQ
LDQM
WE
CAS
RAS
CS
A11
A10
A0
A1
A2
A3
V_CC
2M × 8
1M × 8 × 2 banks
2K/4K
(A0 – A10)
2 (BA)
512 (A0 – A8)
TSOP 2
1
50
V_SS
2
49 DQ15
3
48 DQ14
4
47
V_SSQ
5
46 DQ13
6
45 DQ12
7
44
V_CCQ
8
43 DQ11
9
42 DQ10
10
41
V_SSQ
11
40 DQ9
12
39 DQ8
13
38
V_CCQ
14
37 NC
15
36 UDQM
16
35 CLK
17
34 CKE
18
33 NC
19
32 A9
20
31 A8
21
30 A7
22
29 A6
23
28 A5
24
27 A4
25
26
V_SS
1M × 16
512K × 16 × 2 banks
2K/4K
(A0 – A10)
2 (BA)
256 (A0 – A7)
Symbol
Pin designation
Pin(s)
DQM (2M × 8)
UDQM/LDQM (1M × 16)
A0 to A10
A11
DQ0 to DQ7 (2M × 8)
DQ0 to DQ15 (1M × 16)
RAS
CAS
WE
CS
V_CC, V_CCQ
V_SS, V_SSQ
CLK
CKE
Description
Output disable/write mask
RA0 – 10
Address inputs CA0 – 7 (×16)
CA0 – 8 (×8)
Bank address (BA)
Input/output
Row address strobe
Column address strobe
Write enable
Chip select
Power (3.3V ± 0.3V)
Ground
Clock input
Clock enable
–7
–8
–10
Unit
Bus frequency (CL = 3)
f_Max
143
125
100
MHz
Maximum clock access time (CL = 3)
t_AC
5.5
6
6
ns
Minimum input setup time
t_S
2
2
2
ns
Minimum input hold time
t_H
1.0
1.0
1.0
ns
Row cycle time (CL = 3, BL = 1)
t_RC
70
80
80
ns
Maximum operating current ([×16], RD or
WR, CL = 3), BL = 2
I_CC1
130
100
100
mA
Maximum CMOS standby current, self refresh
I_CC6
1
1
1
mA
5/21/01; v.1.1
Alliance Semiconductor
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