AS4CM4EOQ Datasheet, PDF (1/16 Pages) Alliance Semiconductor Corporation – 4M X 4 CMOS Quad CAS DRAM (EDO) family

March 2001
®
4M ✕ 4 CMOS QuadCAS DRAM (EDO) family
AS4C4M4EOQ
AS4C4M4E1Q
Features
• Organization: 4,194,304 words × 4 bits
• High speed
- 50/60 ns RAS access time
- 25/30 ns column address access time
- 12/15 ns CAS access time
• Low power consumption
- Active: 495 mW max
- Standby: 5.5 mW max, CMOS I/O
• Extended data out
• Refresh
- 4096 refresh cycles, 64 ms refresh interval for
4C4M4EOQ
- 2048 refresh cycles, 32 ms refresh interval for
AS4C4M4E1Q
- RAS-only and hidden refresh or CAS-before-RAS refresh
or self-refresh
• TTL-compatible
• 4 separate CAS pins allow for separate I/O operation
• JEDEC standard package
- 300 mil, 28-pin SOJ
- 300 mil, 28-pin TSOP
• 5V power supply
• Latch-up current ≥ 200 mA
• ESD protection ≥ 2000 mV
Pin arrangement
SOJ
TSOP
V_{CC 1}
I/O0 2
I/O1 3
WE 4
RAS 5
*NC/A11 6
CAS0 ₇
CAS1 8
A10 ₉
A0 10
A1 11
A2 12
A3 13
V_CC 14
28 ^GND
27 ^I/O3
V_{CC 1}
I/O0 2
26 ^I/O2
I/O1 3
25 CAS3
WE 4
24 OE
RAS 5
23 A9
*NC/A11 6
22 CAS2
21 ^NC
CAS0 7
CAS1 8
20 ^A8
19 ^A7
18 ^A6
A10 ₉
A0 10
A1 11
17 A5
A2 12
16 A4
A3 13
15 GND
V_CC 14
* NC on 2K refresh version; A11 on 4K refresh version
28 ^GND
27 ^I/O3
26 ^I/O2
25 CAS3
24 OE
23 A9
22 ^CAS2
21 NC
20 ^A8
19 ^A7
18 ^A6
17 A5
16 A4
15 GND
Pin designation
Pin(s)
Description
A0 to A11
Address inputs
RAS
Row address strobe
CAS
Column address strobe
WE
Write enable
I/O0 to I/O3
Input/output
OE
Output enable
V_CC
GND
Power
Ground
NC
No Connection
Selection guide
Maximum RAS access time
Maximum column address access time
Maximum CAS access time
Maximum output enable (OE) access time
Minimum read or write cycle time
Minimum hyper page mode cycle time
Maximum operating current
Maximum CMOS standby current
Symbol
t_RAC
t_CAA
t_CAC
t_OEA
t_RC
t_PC
I_CC1
I_CC5
4C4M4EOQ/E1Q-50
50
25
12
13
85
20
110
1.0
3/22/01; v.1.0
Alliance Semiconductor
4C4M4EOQ/E1-60
Unit
60
ns
30
ns
15
ns
15
ns
100
ns
24
ns
100
mA
1.0
mA
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