AS4C8M16SA-6TIN Datasheet, PDF (1/54 Pages) Alliance Semiconductor Corporation – 128M - 8M x 16 bit Synchronous DRAM (SDRAM)

AS4C8M16SA
Confidential
128M - 8M x 16 bit Synchronous DRAM (SDRAM)
(Rev. 2.2, March 2014)
Features
 ^{Fast access time from clock: 5/5.4 ns}
 ^{Fast clock rate: 166/143 MHz}
 ^{Fully synchronous operation}
 ^{Internal pipelined architecture}
 ^{2M word x 16-bit x 4-bank}
 ^{Programmable Mode registers}
- CAS Latency: 2, or 3
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: Sequential or Interleaved
- Burst stop function
 ^{Operating temperature range}
- Commercial (0 ~ 70°C)
- Industrial (-40 ~ 85°C)
 ^{Auto Refresh and Self Refresh}
 ^{4096 refresh cycles/64ms}
 ^{CKE power down mode}
 ^{Single +3.3V  0.3V power supply}
 ^{Interface: LVTTL}
 ^{54-pin 400 mil plastic TSOP II package}
 ^{54-ball 8.0 x 8.0 x 1.2mm (max) FBGA package}
All parts ROHS Compliant
Overview
The 128Mb SDRAM is a high-speed CMOS
synchronous DRAM containing 128 Mbits. It is
internally configured as 4 Banks of 2M word x 16
DRAM with a synchronous interface (all signals are
registered on the positive edge of the clock signal,
CLK). Read and write accesses to the SDRAM are
burst oriented; accesses start at a selected location
and continue for a programmed number of locations
in a programmed sequence. Accesses begin with
the registration of a BankActivate command which
is then followed by a Read or Write command.
The SDRAM provides for programmable Read
or Write burst lengths of 1, 2, 4, 8, or full page, with
a burst termination option. An auto precharge
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst
sequence. The refresh functions, either Auto or Self
Refresh are easy to use.
By having a programmable mode register, the
system can choose the most suitable modes to
maximize its performance. These devices are well
suited for applications requiring high memory
bandwidth and particularly well suited to high
performance PC applications.
Table 1. Key Specifications
AS4C16M16S
tCK3 Clock Cycle time (min.)
tAC3 Access time from CLK (max.)
tRAS Row Active time (min.)
tRC Row Cycle time (min.)
-6/7
6/7 ns
5.4/5.4 ns
42/42 ns
60/63 ns
Table 2. Ordering Information
Part Number
Frequency
Package
AS4C8M16SA-7TCN
143 MHz
54 pin TSOP II
AS4C8M16SA-6TCN
AS4C8M16SA-6TIN
166 MHz
166 MHz
54 pin TSOP II
54 pin TSOP II
AS4C8M16SA-6BIN
AS4C8M16SA-7BCN
T : indicates TSOP II package
B : indicates TFBGA package
166 MHz
143 MHz
54 ball TFBGA
54 ball TFBGA
N : indicates Pb free and Halogen free – ROHS compliant parts
C: Commercial I: Industrial
Confidential
1
Rev. 2.2
Mar /2014