AS4C64M16MD1 Datasheet, PDF (1/41 Pages) Alliance Semiconductor Corporation – AS4C64M16MD1

AS4C64M16MD1
Confidential
1 Gb (64M x 16 bit) 1.8v High Performance Mobile DDR SDRAM
Advanced (Rev. 1.0, Mar. /2014)
Features
Description
- 4 banks x 16M x 16 organization
The AS4C64M16MD1 is a four bank mobile DDR
- Data Mask for Write Control (DM)
DRAM organized as 4 banks x 16M x 16. It
- Four Banks controlled by BA0 & BA1
achieves high speed data transfer rates by
- Programmable CAS Latency: 2, 3
employing a chip architecture that prefetches
- Programmable Wrap Sequence: Sequential
multiple bits and then synchronizes the output data
or Interleave
to a system clock.
- Programmable Burst Length:
2, 4, 8 or 16 for Sequential Type
2, 4, 8 or 16 for Interleave Type
- Automatic and Controlled Precharge Command
- Power Down Mode
All of the control, address, circuits is synchronized
with the positive edge of an externally sup- plied
clock. I/O transactions are possible on both edges
of DQS.
- Auto Refresh and Self Refresh
Operating the four memory banks in an
- Refresh Interval: 8192 cycles/64ms
interleaved fashion allows random access
- Double Data Rate (DDR)
operation to occur at a higher rate than is possible
- Bidirectional Data Strobe (DQS) for input and
with standard DRAMs. A sequential and gapless
output data, active on both edges
data rate is possible depending on burst length,
- Differential clock inputs CLK and /CLK
CAS latency and speed grade of the device.
- Power Supply 1.7V - 1.95V
- Drive Strength (DS) Option: Full, 1/2, 1/4, 1/8
- Auto Temperature-Compensated Self Refresh
(Auto TCSR)
- Partial-Array Self Refresh (PASR) Option: Full,
Additionally, the device supports low power saving
features like PASR, Auto-TCSR, DPD as well as
options for different drive strength. It’s ideally suit-
able for mobile application.
1/2, 1/4, 1/8, 1/16
- Deep Power Down (DPD) mode
6
Unit
- Operating Temperature Range
• Extended -25°C to 85°C
• Industrial -40°C to 85°C
- 60 ball FPBGA package
ALL PRODUCTS ROHS COMPLIANT
System Frequency (fCK)
166 MHz
MHz
Clock Cycle Time (tCK3)
6
ns
Output data access Time
(tAC _(CL3))
.05.
ns
0
ORDERING INFORMATION
Part No.
Clock Frequency Vdd/Vddq Organisation
Package
AS4C64M16MD1-6BCN* DDR333
1.8V/1.8V 16M x 16 Bits x 4 Banks 60-FPBGA
166MHz
AS4C64M16MD1-6BIN* DDR333
1.8V/1.8V 16M x 16 Bits x 4 Banks 60-FPBGA
166MHz
*B = FPBGA package
* C = usually represents commercial temperature but in this case it Extended (-25°C to +85°C) I = Industrial temperature -40°C to 85°C
* N = ROHS Compliant
Confidential
1
Rev 1.0 Mar/2014