AS4C4M16SA-AUTOMOTIVE Datasheet, PDF (1/54 Pages) Alliance Semiconductor Corporation – Fully synchronous operation

AS4C4M16SA-Automotive
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64M – (4M x 16 bit) Synchronous DRAM (SDRAM)
Advanced (Rev. 1.0- 63nm, Mar. /2014)
Features
 ^{Fast access time from clock: 5.4 ns}
 ^{Fast clock rate: 166 MHz}
 ^{Fully synchronous operation}
 ^{AEC-Q100 Compliant}
 ^{Internal pipelined architecture}
 ^{1M word x 16-bit x 4-bank}
 ^{Programmable Mode registers}
- CAS Latency: 2 or 3
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: Sequential or Interleaved
- Burst stop function
- Optional drive strength control
 ^{Auto Refresh and Self Refresh}
 ^{4096 refresh cycles/32ms}
 ^{Automotive Ambient Temperature: -40~105°C}
 ^{CKE power down mode}
 ^{Single +3.3V  0.3V power supply}
 ^{Interface: LVTTL}
 54-pin 400 mil plastic TSOP II package
 ^{54-ball 8.0 x 8.0 x 1.2mm (max) FBGA package}
- All parts ROHS Compliant
Overview
The 64Mb SDRAM is a high-speed CMOS
synchronous DRAM containing 64 Mbits. It is internally
configured as 4 Banks of 1M word x 16 DRAM with a
synchronous interface (all signals are registered on
the positive edge of the clock signal, CLK). Read and
write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Accesses begin with the registration of a
Bank Activate command which is then followed by a
Read or Write command.
The SDRAM provides for programmable Read or
Write burst lengths of 1, 2, 4, 8, or full page, with a
burst termination option. An auto precharge function
may be enabled to provide a self-timed row precharge
that is initiated at the end of the burst sequence. The
refresh functions, either Auto or Self Refresh are easy
to use. By having a programmable mode register, the
system can choose the most suitable modes to
maximize its performance. These devices are well
suited for applications requiring high memory
bandwidth and particularly well suited to high
performance PC applications.
Table 1. Key Specifications
AS4C4M16SA
tCK3
Clock Cycle time(min.)
tAC3 Access time from CLK (max.)
tRAS Row Active time(min.)
tRC
Row Cycle time(min.)
-6
6 ns
5.4 ns
42ns
60ns
Table 2.Ordering Information
Part Number
Frequency
AS4C4M16SA-6BAN
166MHz
AS4C4M16SA-6TAN
166MHz
Package
54-Ball FBGA
54-Pin TSOPII
Temperature Temp Range
Industrial
-40 ~ 105°C
Industrial
-40 ~ 105°C
B: indicates FBGA package T: indicates TSOP II package
N: indicates Pb and Halogen Free
Confidential
1
Rev. 1.0-63nm
Mar. /2014