3957 Datasheet, PDF (9/16 Pages) Allegro MicroSystems – FULL-BRIDGE PWM MICROSTEPPING MOTOR DRIVER

3957
FULL-BRIDGE PWM
MICROSTEPPING
MOTOR DRIVER
Functional Description
Two A3957S— full-bridge PWM microstepping motor
drivers are needed to drive the windings of a bipolar stepper
motor. Internal pulse-width modulated (PWM) control circuitry
regulates each motor winding’s current. The peak motor
current is set by the value of an external current-sense resistor
(R_S), a reference voltage (V_REF), and the digital-to-analog
converter (DAC) data inputs (D₀, D₁, D₂, and D₃).
To improve motor performance, especially when using
sinusoidal current profiles necessary for microstepping, the
A3957S— has three distinct current-decay modes: slow decay,
fast decay, and mixed decay.
PHASE Input. The PHASE input controls the direction of
current flow in the load (table 1). An internally generated dead
time of approximately 1.5 µs prevents crossover currents that
could occur when switching the PHASE input.
DAC Data Inputs (D₀, D₁, D₂, D₃). A non-linear DAC is used
to digitally control the output current. The output of the DAC is
used to set the trip point of the current-sense comparator. Table
3 shows DAC output voltages for each input condition. When
D₁, D₂, and D₃ are all logic low, all of the power output
transistors are turned off.
Internal PWM Current Control. Each motor driver IC
contains an internal fixed off-time PWM current-control circuit
that limits the load current to a desired value (I_TRIP). Initially, a
diagonal pair of source and sink transistors are enabled and
current flows through the motor winding and R_S (figure 1).
V
BB
DRIVE CURRENT
RECIRCULATION
(SLOW-DECAY MODE)
RECIRCULATION
(FAST-DECAY MODE)
RS
Dwg. EP-006-15
Figure 1 — Load-Current Paths
When the voltage across the sense resistor equals the DAC
output voltage, the current-sense comparator resets the PWM
latch, which turns off the source drivers (slow-decay mode) or
the sink and source drivers (fast- or mixed-decay mode).
With the DATA input lines tied to V_CC, the maximum
value of current limiting is set by the selection of R_S and V_REF
with a transconductance function approximated by:
I_TRIP ≈ V_REF/3R_S = I_OUT + I_SO.
where I_SO is the sense-current offset due to the base-drive
current of the sink transistor (typically 30 mA). The actual peak
load current (I_PEAK) will be slightly higher than I_TRIP due to
internal logic and switching delays. The driver(s) remain off
for a time period determined by a user-selected external
resistor-capacitor combination (R_TC_T). At the end of the fixed
off time, the driver(s) are re-enabled, allowing the load current
to increase to I_TRIP again, maintaining an average load current.
The current-sense comparator has a fixed offset of approxi-
mately 16 mV. With R_S = 0.5 Ω, the sense-current offset (I_SO)
is effectively cancelled (V_IO(S) ≈ I_SO • R_S).
The DAC data input lines are used to provide up to eight
levels of output current. The internal 4-bit digital-to-analog
converter reduces the reference input to the current-sense
comparator in precise steps (the step reference current ratio or
SRCR) to provide half-step, quarter-step, eighth-step, or
“microstepping” load-current levels.
I_TRIP ≈ SRCR x V_REF/3R_S
Slow Current-Decay Mode. When V_PFD ≥ 3.5 V, the device is
in slow current-decay mode (the source drivers are disabled
when the load current reaches I_TRIP). During the fixed off time,
the load inductance causes the current to recirculate through the
motor winding, sink driver, ground clamp diode, and sense
resistor (see figure 1). Slow-decay mode produces low ripple
current for a given fixed off time (see figure 2). Low ripple
current is desirable because the average current in the motor
winding is more nearly equal to the desired reference value,
resulting in increased motor performance in microstepping
applications.
For a given level of ripple current, slow decay affords the
lowest PWM frequency, which reduces heating in the motor and
driver IC due to a corresponding decrease in hysteretic core
losses and switching losses respectively. Slow decay also has
the advantage that the PWM load current regulation can follow
a more rapidly increasing reference before the PWM frequency
drops into the audible range. For these reasons slow-decay
mode is typically used as long as good current regulation can be
maintained.