A4931 Datasheet, PDF (8/9 Pages) Allegro MicroSystems – The A4931 is a complete 3-phase brushless DC motor pre-driver.

A4931
3-Phase Brushless DC Motor Pre-Driver
by holding ENB high for longer than 3 ms. Note that Brake mode
overrides Standby mode, so hold the BRAKEZ pin high in order
to enter Standby mode.
Charge Pump The internal charge pump is used to generate a
supply above V_BB to drive the high-side MOSFETs. The volt-
age on the VCP pin is internally monitored, and in case of a fault
condition, the outputs of the device are disabled.
Fault Shutdown In the event of a fault due to excessive
junction temperature or due to low voltage on VCP or VBB,
the outputs of the device are disabled until the fault condition is
removed. At power-up the UVLO circuit disables the drivers.
Lock Detect Function The IC will evaluate a locked rotor
condition under either of these two different conditions:
• The FG1 signal is not consistently changing.
• The proper commutation sequence is not being followed. The
motor can be locked in a condition in which it toggles between
two specific Hall device states.
Both of these fault conditions are allowed to persist for period
of time, t_lock. t_lock is set by capacitor connected to CLD pin. C_LD
produces a triangle waveform (1.67 V peak-to-peak) with fre-
quency linearly related to the capacitor value. t_lock is defined as
127 cycles of this triangle waveform, or:
Overvoltage Protection VBB is monitored to determine if
a hazardous voltage is present due to the motor generator pump-
ing up the supply bus. When the voltage exceeds V_BBOV , the
synchronous rectification feature is disabled.
Overtemperature Protection If die temperature exceeds
approximately 170°C, the Thermal Shutdown function will dis-
able the outputs until the internal temperature falls below the
15°C hysteresis.
t_lock = C_LD × 20 s/μF
After the wait time, t_lock , has expired, the outputs are disabled,
and the fault is latched. These fault conditions can only be cleared
by any one of the following actions:
• Rising or falling edge on the DIR pin
• VBB UVLO threshold exceeded (during power-up cycle)
• ENB pin held high for > t_lock / 2
Hall State Reporting The FG1 pin is an open drain output
that changes state at each transition of an external Hall element.
The FG2 pin is an open drain output that changes state at each
HAx transition.
The Lock Detect function can be disabled by connecting CLD to
GND.
When the A4931 is in Brake mode, the Lock Detect counter is
disabled.
Allegro MicroSystems, Inc.
8
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com