A3979 Datasheet, PDF (7/15 Pages) Allegro MicroSystems – Microstepping DMOS Driver with Translator

A3979
DMOS Microstepping Driver with Translator
Timing Requirements
(T_A = +25°C, V_DD = 5 V, Logic Levels are V_DD and Ground)
STEP
50%
C
D
A
B
MS1/MS2/
DIR/RESET
E
SLEEP
A. Minimum Command Active Time
Before Step Pulse (Data Set-Up Time) ..... 200 ns
B. Minimum Command Active Time
After Step Pulse (Data Hold Time) ............ 200 ns
C. Minimum STEP Pulse Width ...................... 1.0 μs
D. Minimum STEP Low Time ......................... 1.0 μs
E. Maximum Wake-Up Time ......................... 1.0 ms
Dwg. WP-042
Figure 1. Logic Interface Timing Diagram
Table 1. Microstep Resolution Truth Table
MS1 MS2 Microstep Resolution Excitation Mode
L
L Full Step
2 Phase
H
L Half Step
1-2 Phase
L
H Quarter Step
W1-2 Phase
H
H Sixteenth Step
4W1-2 Phase
Allegro MicroSystems, Inc.
7
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]
www.allegromicro.com