A3959_16 Datasheet, PDF (7/12 Pages) Allegro MicroSystems – DMOS Full-Bridge PWM Motor Driver

A3959
DMOS Full-Bridge PWM Motor Driver
FUNCTIONAL DESCRIPTION (continued)
Internal Current-Control Mode. Inputs PFD1 and
PFD2 determine the current-decay method after an
overcurrent event is detected at the SENSE input. In slow-
decay mode, both sink drivers are turned on for the fixed
off-time period. Mixed-decay mode starts out in fast-decay
mode for a portion (15% or 48%) of the fixed off time, and
then is followed by slow decay for the remainder of the
period.
PFD2
PFD1
% t_off Decay
0
0
0
Slow
0
1
15
Mixed
1
0
48
Mixed
1
1
100
Fast
PWM Blank Timer. When a source driver turns on, a
current spike occurs due to the reverse-recovery currents
of the clamp diodes and/or switching transients related to
distributed capacitance in the load. To prevent this current
spike from erroneously resetting the source-enable latch,
the sense comparator is blanked. The blank timer runs
after the off-time counter to provide the blanking function.
The blank timer is reset when ENABLE is chopped or
PHASE is changed. For external PWM control, a PHASE
change or ENABLE on will trigger the blanking function.
The duration is determined by the BLANK input and the
oscilator.
BLANK
t_blank
0
6/f_osc
1
12/f_osc
Synchronous Rectification. When a PWM off cycle
is triggered, either by an ENABLE chop command or
internal fixed off-time cycle, load current will recirculate
according to the decay mode selected by the control logic.
The A3959 synchronous rectification feature will turn on
the appropriate pair of DMOS outputs during the current
decay and effectively short out the body diodes with the
low r_DS(on) driver. This will reduce power dissipation
significantly and can eliminate the need for external
Schottky diodes.
Synchronous rectification will prevent reversal of load
current by turning off all outputs when a zero-current level
is detected.
Shutdown. In the event of a fault (excessive junction
temperature, or low voltage on CP or V_REG) the outputs of
the device are disabled until the fault condition is removed.
At power up, and in the event of low V_DD, the UVLO
circuit disables the drivers.
Braking. The braking function is implemented by
driving the device in slow-decay mode via EXTMODE
and applying an enable chop command. Because it is
possible to drive current in either direction through the
DMOS drivers, this configuration effectively shorts out
the motor-generated BEMF as long as the ENABLE
chop mode is asserted. It is important to note that the
internal PWM current-control circuit will not limit the
current when braking, because the current does not flow
through the sense resistor. The maximum brake current
can be approximated by V_BEMF/R_L. Care should be taken
to ensure that the maximum ratings of the device are not
exceeded in worst-case braking situations of high speed
and high inertial loads.
SLEEP Logic. The SLEEP input terminal is used to
minimize power consumption when when not in use.
This disables much of the internal circuitry including the
regulator and charge pump. Logic low will put the device
into sleep mode, logic high will allow normal operation.
Note: If the sleep mode is not used, connect a 5 kΩ pull-
up resistor between the SLEEP terminal and V_DD.
Allegro MicroSystems, LLC
7
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com