3977 Datasheet, PDF (7/18 Pages) Allegro MicroSystems – MICROSTEPPING DMOS DRIVER WITH TRANSLATOR

3977
MICROSTEPPING DMOS DRIVER
WITH TRANSLATOR
Functional Description (cont’d)
Fixed Off-Time. The internal PWM current-control
circuitry uses a one shot to control the time the driver(s)
remain(s) off. The one shot off-time, t_off, is determined by
the selection of an external resistor (R_T) and capacitor
(C_T) connected from the RC timing terminal to ground.
The off time, over a range of values of C_T = 470 pF to
1500 pF and R_T = 12 kΩ to 100 kΩ is approximated by:
t_off = R_TC_T
RC Blanking. In addition to the fixed off time of the
PWM control circuit, the C_T component sets the compara-
tor blanking time. This function blanks the output of the
current-sense comparator when the outputs are switched
by the internal current-control circuitry. The comparator
output is blanked to prevent false over-current detection
due to reverse recovery currents of the clamp diodes, and/
or switching transients related to the capacitance of the
load. The blank time t_BLANK can be approximated by:
t_BLANK = 1400C_T
Charge Pump. (CP₁ and CP₂). The charge pump is
used to generate a gate supply greater than V_BB to drive
the source-side DMOS gates. A 0.22 µF ceramic capaci-
tor should be connected between CP₁ and CP₂ for pump-
ing purposes. A 0.22 µF ceramic capacitor is required
between V_CP and V_BB to act as a reservoir to operate the
high-side DMOS devices.
V_REG. This internally generated voltage is used to operate
the sink-side DMOS outputs. The V_REG terminal should
be decoupled with a 0.22 µF capacitor to ground. V_REG is
internally monitored and in the case of a fault condition,
the outputs of the device are disabled.
Enable Input (ENABLE). This active-low input
enables all of the DMOS outputs. When logic high the
outputs are disabled. Inputs to the translator (STEP,
DIRECTION, MS₁, MS₂) are all active independent of the
ENABLE input state.
Shutdown. In the event of a fault (excessive junction
temperature, or low voltage on V_CP) the outputs of the
device are disabled until the fault condition is removed.
At power up, and in the event of low V_DD, the under-
voltage lockout (UVLO) circuit disables the drivers and
resets the translator to the HOME state.
Sleep Mode (SLEEP). An active-low control input
used to minimize power consumption when not in use.
This disables much of the internal circuitry including the
output DMOS, regulator, and charge pump. A logic high
allows normal operation and startup of the device in the
home position. When coming out of sleep mode, wait
1 ms before issuing a STEP command to allow the charge
pump (gate drive) to stabilize.
Percent Fast Decay Input (PFD). When a STEP
input signal commands a lower output current from the
previous step, it switches the output current decay to either
slow-, fast-, or mixed-decay depending on the voltage
level at the PFD input. If the voltage at the PFD input is
greater than 0.6V_DD then slow-decay mode is selected. If
the voltage on the PFD input is less than 0.21V_DD then
fast-decay mode is selected. Mixed decay is between
these two levels. This terminal should be decoupled with
a 0.1 µF capacitor.
Mixed Decay Operation. If the voltage on the PFD
input is between 0.6V_DD and 0.21V_DD, the bridge will
operate in mixed-decay mode depending on the step
sequence (see figures). As the trip point is reached, the
device will go into fast-decay mode until the voltage on
the RC terminal decays to the voltage applied to the PFD
terminal. The time that the device operates in fast decay is
approximated by:
t_FD = R_TC_TIn (0.6V_DD/V_PFD)
After this fast decay portion, t_FD, the device will
switch to slow-decay mode for the remainder of the fixed
off-time period.
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