A3968SLBTR Datasheet, PDF (6/8 Pages) Allegro MicroSystems – Dual Full-Bridge PWM Motor Driver

A3968
Dual Full-Bridge PWM Motor Driver with Brake
FUNCTIONAL DESCRIPTION
Internal PWM Current Control. The A3968 dual
full-bridges bidirectionally control two DC motors. An
internal fixed-frequency PWM control circuit controls the
the load current in each motor. The current-control circuitry
works as follows: when the outputs of the full-bridge are
turned on, current increases in the motor winding. The load
current is sensed by the current-control comparator via
an external sense resistor. R_S. Load current continues to
increase until it reaches the predetermined value, set by the
selection of external current-sensing resistors and reference
input voltage (V_REF) according to the equation:
I_TRIP = I_OUT + I_SO = V_REF/(4 R_S)
where I_SO is the sense-current error (typically 18 mA) due
to the base-drive current of the sink driver transistor.
At the trip point, the comparator resets the source-en-
able latch, turning off the source driver of that full-bridge.
The source turn-off of one full-bridge is independent of
the other full-bridge. Load inductance causes the current to
recirculate through the sink driver and ground-clamp diode.
The current decreases until the internal clock oscillator sets
the source-enable latches of both Full-bridges, turning on
the source drivers of both bridges. Load current increases
again, and the cycle is repeated.
The frequency of the internal clock oscillator is set by
the external timing components R_TC_T. The frequency can
be approximately calculated as:
f_osc = 1/(R_T C_T + t_blank)
where t_blank is defined below.
The range of recommended values for R_T and C_T are
20 to 100 k and 470 to 1000 pF respectively. Nominal
values of 56 k and 680 pF result in a clock frequency of
25.4 kHz.
Current-Sense Comparator Blanking. When the
source driver is turned on, a current spike occurs due to the
reverse-recovery currents of the clamp diodes and switch-
ing transients related to distributed capacitance in the load.
To prevent this current spike from erroneously resetting the
source enable latch, the current-control comparator output
is blanked for a short period of time when the source driver
is turned on. The blanking time is set by the timing compo-
nent C_T according to the equation:
t_blank = 1900 C_T (μs).
A nominal C_T value of 680 pF will give a blanking time
of 1.3 μs.
The current-control comparator is also blanked when
the load current changes polarity (direction or phase
change). This internally generated blank time is approxi-
mately 1.8 μs.
V _PHASE
+
I _OUT 0
–
BRIDGE
ON
See Enlargement A
ALL
OFF
BRIDGE
ON
Enlargement A
INTERNAL
OSCILLATOR
I _TRIP
t_d
R_TC_T
SOURCE
OFF
t_blank
Dwg. WM-003-2
V
BB
BRIDGE ON
SOURCE OFF
ALL OFF
RS
Dwg. EP-006-16
Allegro MicroSystems, LLC
6
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]
www.allegromicro.com