A4930 Datasheet, PDF (5/9 Pages) Allegro MicroSystems – Designed for pulse width modulated (PWM) current control of single phase brushless fans, the A4930 minimizes external component count and integrates all the key features required...

A4930
Single Phase Fan Pre-Driver
Functional Description
VREG5 This pin should be decoupled with a 0.1 μF capacitor
to ground. VREG5 can supply up to 15 mA, which can used to
power the external Hall element.
VREG8 This pin should be decoupled with a 0.1 μF capacitor to
ground. VREG8 is used to power the low-side gate drive circuits.
Charge Pump The charge pump is used to generate a supply
above V_BB to drive the high-side MOSFETs. The VCP voltage
is internally monitored, and in the case of a fault condition, the
outputs of the device are disabled.
Lock Detect The IC detects a locked rotor condition by checking
to ensure that the FG output signal is continuously changing. The
length of time allowed for a stoppage before evaluating a locked
condition, t_LD, is set by capacitor connected to CLD pin. C_LD pro-
duces a triangle waveform with a frequency that is linearly related
to the capacitor value. The definition of t_LD is defined as 8 cycles
of this triangle waveform, and its value can be calculated as:
t_LD = C_LD × (10 s / μF) .
(1)
If an FG transition is not detected within t_LD, the IC will disable
the appropriate source driver and hold both sink drivers on. The
circuit will automatically retry with a 15:1 ratio of off-time to on-
time. An RD pin logic high indicates this fault condition.
Current Limit and Soft Start To minimize demand on the
power supply, peak current is controlled. Initially, with the fan
at a stand-still, the turn-on of the bridge results in current rising
according to the L/R time constant of the motor. To prevent over-
stress, this peak current is regulated by an internal PWM control
circuit. When the outputs of the full-bridge are turned on, current
increases in the motor winding until it reaches a value given by:
I_TRIP = V_REF / 5 × R_SENSE .
(2)
The R_SENSE value should be chosen to keep the peak sense voltage
within the range of 200 to 500 mV, according to the relationship:
R_SENSE < 500 mV / I_{TRIP .}
(3)
At the trip point, the sense comparator resets the source enable
latch, turning off the source driver. At this point, load inductance
causes the current to recirculate for 50 μs.
A soft start capacitor, CSS, can be connected to the SS pin to set
the rate for slowly ramping-up the load current to the maximum
value, according to the relationship:
t_SS = (C_SS × V_REF) / 3.3E–6 _.
(4)
In this case the current limit will likely not be achieved and there
will be less demand on the input power supply. If this feature is
not utilized, the SS pin should be left open.
Synchronous Rectification When a PWM off-cycle is triggered,
load current recirculates. The A4930 synchronous rectification
feature turns on the appropriate MOSFETs during current decay,
and effectively shorts out the body diodes of the low R_DS(on)
driver.
TSD If the die temperature exceeds approximately 165°C, the
outputs will be disabled until the internal temperature falls below
a hysteresis level of 15°C.
Shutdown In the event of a fault due to excessive junction
temperature, or low voltage on VCP or VBB, the outputs of
the device are disabled until the fault condition is removed. At
power-up the UVLO circuit disables the drivers until the UVLO
threshold is reached.
CPWM This capacitor sets the frequency of the internal PWM
circuit. The value is typically from 15 to 30 kHz.
PWM The IC accepts a direct input PWM signal with a level in
the range from 0 to 6 V. The duty cycle, DC, of the input to this
pin is converted to an analog voltage that is output on the SIN
terminal as follows:
V_SIN = 3.5 V –2 × DC .
(5)
If the PWM input is not used, then leave this pin open circuit.
Direct external PWM control can be utilized by applying the
signal to the SIN input (refer to the Applications Information sec-
tion). This can be implemented to create different PWM input to
PWM output transfer functions.
Allegro MicroSystems, Inc.
5
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com