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A5995 Datasheet, PDF (4/12 Pages) Allegro MicroSystems – DMOS Dual Full-Bridge PWM Motor Driver
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A5995
DMOS Dual Full-Bridge PWM Motor Driver
ELECTRICAL CHARACTERISTICS1: Valid at TA = 25 °C, VBB = 40 V, unless otherwise noted
Characteristics
Symbol
Test Conditions
Min.
Typ.2
Max.
Units
Load Supply Voltage Range
Output On-Resistance
Vf , Outputs
Output Leakage
VBB Supply Current
VBB
Operating
8
–
40
V
RDS(on)
Source driver, IOUT = –1.2 A, TJ = 25°C
Sink driver, IOUT = 1.2 A, TJ = 25°C
–
250
300
mΩ
–
240
300
mΩ
IOUT = 1.2 A
–
–
1.2
V
IDSS
Outputs, VOUT = 0 to VBB
–20
–
20
µA
IOUT = 0 mA, outputs on, fPWM = 50 kHz,
duty cycle = 50%
–
–
23
mA
IBB
Outputs off
–
11.7
14
mA
Sleep mode
–10
<1
10
µA
Output Driver Slew Rate
Control Logic
SROUT
10% to 90%
50
100
150
ns
Logic Input Voltage
Logic Input Current
Input Hysteresis
Sleep Rising Threshold
Sleep Falling Threshold
Sleep Hysteresis
Sleep Input Current
VIN(1)
VIN(0)
IIN
Vhys
VSLEEPn(r)
VSLEEPn(f)
VSLEEPn(hys)
ISLEEPn
VIN = 0 to 5 V
PWM change to source on
2
–
–
V
–
–
0.8
V
–20
<1
20
µA
150
300
500
mV
2.5
2.7
2.95
V
–
2.4
–
V
250
325
450
mV
–
100
150
µA
550
700
1000
ns
Propagation Delay Times
PWM change to source off
tpd
PWM change to sink on
35
–
450
ns
550
700
1000
ns
PWM change to sink off
35
–
450
ns
Crossover Delay
Blank Time (DC motor driver)
VREFx Pin Input Voltage Range
VREFx Pin Reference Input Current
Current Trip-Level Error
Protection Circuits
tCD
tBLANK
VREFx
IREF
VERR
Operating
VREF = 1.5 V
VREF = 1.5 V
250
425
1000
ns
2.5
3.2
4
µs
0
–
1.5
V
–
–
±1
μA
–5
–
5
%
VBB UVLO Threshold
VUV(VBB)
VBB rising
7.3
7.6
7.9
V
VBB Hysteresis
VUV(VBB)hys
400
500
600
mV
Overcurrent Protection Threshold
IOVP
3.2
–
–
A
Thermal Shutdown Temperature
TJTSD
155
165
175
°C
Thermal Shutdown Hysteresis
TJTSDhys
–
15
–
°C
1 For input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin.
2 Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for indi-
vidual units, within the specified maximum and minimum limits.
3 VERR = [(VREF/3) – VSENSE] / (VREF/3).
Allegro MicroSystems, LLC
4
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
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