5811 Datasheet, PDF (4/8 Pages) Allegro MicroSystems – BiMOS II 12-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS

5811
BiMOS II 12-BIT
SERIAL-INPUT,
LATCHED SOURCE DRIVERS
CLOCK
DATA IN
STROBE
A
D
B
E
F
C
BLANKING
G
OUT_N
Dwg. No. 12,649A
TIMING REQUIREMENTS
(T_A = +25°C,V_DD = 5 V, Logic Levels are V_DD and Ground)
A. Minimum Data Active Time Before Clock Pulse
(Data Set-Up Time) .......................................................................... 75 ns
B. Minimum Data Active Time After Clock Pulse
(Data Hold Time) ............................................................................. 75 ns
C. Minimum Data Pulse Width ................................................................ 150 ns
D. Minimum Clock Pulse Width ............................................................... 150 ns
E. Minimum Time Between Clock Activation and Strobe ....................... 300 ns
F. Minimum Strobe Pulse Width ............................................................. 100 ns
G. Typical Time Between Strobe Activation and
Output Transistion ......................................................................... 500 ns
Timing is representative of a 3.3 MHz clock. Higher speeds may be attainable
with increased supply voltage; operation at high temperatures will reduce the
specified maximum clock frequency.
Serial Data present at the input is transferred
to the shift register on the logic “0” to logic “1”
transition of the CLOCK input pulse. On
succeeding CLOCK pulses, the registers shift data
information towards the SERIAL DATA OUT-
PUT. The SERIAL DATA must appear at the
input prior to the rising edge of the CLOCK input
waveform.
Information present at any register is trans-
ferred to the respective latch when the STROBE
is high (serial-to-parallel conversion). The
latches will continue to accept new data as long as
the STROBE is held high. Applications where
the latches are bypassed (STROBE tied high) will
require that the BLANKING input be high during
serial data entry.
When the BLANKING input is high, the
output source drivers are disabled (OFF); the
DMOS sink drivers are ON, the information
stored in the latches is not affected by the
BLANKING input. With the BLANKING input
low, the outputs are controlled by the state of
their respective latches.
TRUTH TABLE
Serial
Shift Register Contents
Data Clock
Input Input I₁ I₂ I₃ ... I_N-1 I_N
Serial
Data Strobe
Output Input
Latch Contents
Output Contents
I₁ I₂ I₃ ... I_N-1 I_N Blanklng I₁ I₂ I₃ ... I_N-1 I_N
H
H R₁ R₂ ... R_N-2 R_N-1 R_N-1
L
L R₁ R₂ ... R_N-2 R_N-1 R_N-1
X
R₁ R₂ R₃ ... R_N-1 R_N
R_N
X X X ... X X
X
L
R₁ R₂ R₃ ... R_N-1 R_N
P₁ P₂ P₃ ... P_N-1 P_N
P_N
H
P₁ P₂ P₃ ... P_N-1 P_N
L
P_N
X X X ... X X
H
L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State
P₁ P₂ P₃ ... P_N-1
L L L ... L L
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]