5881 Datasheet, PDF (3/4 Pages) Allegro MicroSystems – BiMOS II DUAL 8-BIT LATCHED DRIVER WITH READ BACK

5881
BiMOS II DUAL
8-BIT LATCHED DRIVER
ELECTRICAL CHARACTERISTICS at T_A = 25°C, V_DD = 5 V (unless otherwise noted).
Characteristic
Output Leakage Current
Output Saturation Voltage
Output Sustaining Voltage
Input Voltage
Input Current
Readback Output Voltage
Logic Supply Current
Clamp Diode Leakage Current
Clamp Diode Forward Voltage
Symbol
I_CEX
V_CE(SAT)
V_CE(sus)
V_IN(0)
V_IN(1)
I_IN(0)
I_IN(1)
V_OUT(1)
V_OUT(0)
l_DD
I_R
V_F
Test Conditions
V_OUT = 20 V
I_OUT = 10 mA
I_OUT = 25 mA
I_OUT = 25 mA, L = 2 mH
V_IN = 0.8 V
V_IN = 5 V
I_OUT = -400 µA
I_OUT = 5.0 mA
All Drivers ON
All Drivers OFF
V_R = 20 V
I_F = 50 mA
Min.
—
—
—
15
-0.3
3.5
—
—
3.5
—
—
—
—
—
Limits
Max.
50
0.1
0.5
—
0.8
5.3
-10
10
—
0.8
14
3.0
50
1.5
Units
µA
V
V
V
V
V
µA
µA
V
V
mA
mA
µA
V
Dwg. No. A-14,228
TIMING CONDITIONS
(V_DD = 5.0 V, Logic Levels are V_DD and Ground)
A. Minimum Data Active Time Before Strobe Enabled
(Data Set-Up Time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ns
B. Minimum Data Active Time After Strobe Disabled
(Data Hold Time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ns
C. Minimum Strobe Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 ns
D. Typical Time Between Strobe Activation and Output
ON to OFF Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 µs
E. Typical Time Between Strobe Activation and Output
OFF to ON Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 ns
F. Minimum Clear Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 ns
G. Minimum Data Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 ns
A high on the READ/WRITE input allows
the circuit to accept data in. Information then
present at an input is transferred to its latch
when the STROBE is high. A high CLEAR
input will set all latches to the output OFF
condition regardless of the data or STROBE
input levels. A high OUTPUT ENABLE will
set all outputs to the OFF condition regard-
less of any other input conditions. When the
OUTPUT ENABLE is low, the outputs de-
pend on the state of their respective latches.
A low on the READ/WRITE input will
allow the latched data to be read back on the
data input lines. Allow a minimum of 750 ns
delay (will increase with capacitive loading)
before reading back the state of the latches.
The read back feature is for error checking
applications and allows the system to verify
that data has been received and latched.