5815 Datasheet, PDF (3/6 Pages) Allegro MicroSystems – BiMOS II 8-BIT LATCHED SOURCE DRIVERS

UCN5815EP
5815
BiMOS II
8-BIT LATCHED
SOURCE DRIVERS
Dwg. No. A-10,991
TIMING CONDITIONS
(V_DD = 5 V, T_A = +25°C, Logic Levels are V_DD and Ground)
Dwg. No. A-14,357
Information present at an input is trans-
ferred to its latch when the STROBE and
ENABLE are high. The latches will continue
to accept new data as long as both STROBE
and ENABLE are held high. With either
STROBE or ENABLE in the low state, no
information can be loaded into the latches.
When the BLANKING input is high, all
of the output buffers are disabled (off)
without affecting the information stored in
the latches. With the BLANKING input low,
the outputs are controlled by the state of the
latches.
A. Minimum Data Active Time Before Strobe Enabled
(Data Set-Up Time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ns
B. Minimum Data Active Time After Strobe Disabled
(Data Hold Time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ns
C. Minimum Strobe Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 ns
D. Typical Time Between Strobe Activation and Output
ON to OFF Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0 µs
E. Typical Time Between Strobe Activation and Output
OFF to ON Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 ns
F. Minimum Data Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 ns
Timing is representative of a 4.4 MHz data input rate. Higher speeds may be
attainable with increased supply voltage; operation at high temperatures will
reduce the specified maximum clock frequency.
TRUTH TABLE
INPUTS
IN_N
STROBE
ENABLE
BLANK
0
1
1
0
1
1
1
0
X
X
X
1
X
0
X
0
X
0
X
0
X
X
0
0
X
X
0
0
OUT_N
T-1 T
X
0
X
1
X
0
1
1
0
0
1
1
0
0
X = irrelevant
T-1 = previous output state
T = present output state