A8502 Datasheet, PDF (28/35 Pages) Allegro MicroSystems – Wide Input Voltage Range, High Efficiency

A8502
Wide Input Voltage Range, High Efficiency
Fault Tolerant LED Driver
The reverse voltage rating should be such that during operation
condition, the voltage rating of the device is larger than the maxi-
mum output voltage. In this case it is V_OUT(OVP).
The peak current through the diode is calculated as:
I_dp = I_IN(max) + ¹/₂ ΔI_Lused
(23)
= 0.94 (A) + 0.36 (A) / 2 = 1.12 A
The third major component in deciding the switching diode is the
reverse current, I_R , characteristic of the diode. This characteristic
is especially important when PWM dimming is implemented.
During PWM off-time the boost converter is not switching. This
results in a slow bleeding off of the output voltage, due to leakage
currents. I_R can be a large contributor, especially at high tempera-
tures. On the diode that was selected in this design, the current
varies between 1 and 100 μA.
Step 7 Choosing the output capacitors. The output capacitors
must be chosen such that they can provide filtering for both the
boost converter and for the PWM dimming function. The biggest
factors that contribute to the size of the output capacitor are:
PWM dimming frequency and PWM duty cycle. Another major
contributor is leakage current, I_LK . This current is the combina-
tion of the OVP leakage current as well as the reverse current of
the switching diode. In this design the PWM dimming frequency
is 200 Hz and the minimum duty cycle is 1%. Typically, the volt-
age variation on the output, V_COUT , during PWM dimming must
be less than 250 mV, so that no audible hum can be heard. The
capacitance can be calculated as follows:
C_OUT = I_LK
1 – D(min)
f_{PWM(dimming) VCOUT}
(24)
= 200 (μA)
1 – 0.01
= 3.96 μF
200 (Hz) 0.250 (V)
The rms current through the capacitor is given by:
I_COUTrms = I_OUT
D(max)
+
∆I_Lused
I_IN(max)×
12
(25)
1 – D(max)
= 0.240 (A)
0.72
+
0.36 (A)
0.94 (A) × 12
= 0.39 A
1 – 0.72
The output capacitor must have a current rating of at least
390 mA. The capacitor selected in this design was a 4.7 μF 50 V
capacitor with a 3 A current rating.
Step 8 Selecting input capacitor. The input capacitor must be
selected such that it provides a good filtering of the input voltage
waveform. A good estimation rule is to set the input voltage rip-
ple, ΔV_IN , to be 1% of the minimum input voltage. The minimum
input capacitor requirements are as follows:
C_IN = ₈
∆I_Lused
f_{SW ∆VIN}
(26)
=
0.36 (A)
= 0.23 μF
8 2 (MHz) 0.1 (V)
The rms current through the capacitor is given by:
C_INrms ₌
I_OUT
×
∆I_Lused
I_IN(max)
(27)
(1 – D)× 12
0.240 (A) ×
0.36 (A)
0.94 (A)
=
= 0.095 A
(1 – 0.72)× ₁₂
A capacitor larger than 3.96 μF should be selected due to degra-
dation of capacitance at high voltages on the capacitor. A ceramic
4.7 μF 50 V capacitor is a good choice to fulfill this requirement.
Corresponding capacitors include:
A good ceramic input capacitor with ratings of 2.2 μF 50 V or
4.7 μF 50 V will suffice for this application. Corresponding
capacitors include:
Vendor
Murata
Murata
Value
4.7 μF 50 V
2.2 μF 50 V
Part number
GRM32ER71H475KA88L
GRM31CR71H225KA88L
Vendor
Murata
Murata
Value
4.7 μF 50 V
2.2 μF 50 V
Part number
GRM32ER71H475KA88L
GRM31CR71H225KA88L
Allegro MicroSystems, Inc.
28
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com